3.11.1. Programmer's model

Programming details for the EBM are described in the following sections:

Example AHB-Lite core

Figure 3.18 shows the example AHB-Lite core.

Figure 3.18. Example AHB-Lite core

The core is completely synchronous with the AHB bus clock signal, HCLK, and is reset by the AHB reset signal, HRESETn. Read transfers are not locked, but HMASTLOCK is asserted HIGH to lock write transfers. The HREADY signal stalls the core.

In AHB-Lite, SPLIT and RETRY responses are not supported, so only HRESP[0] must be decoded and used in the core. However, it is safer to decode the full HRESP[1:0] signal. When this signal indicates an ERROR response during a read operation, the corresponding data is ignored.

The core consists of a counter, burst generation logic, and a 4x32 or 64-bit register bank. From a power-up or reset state, it uses the counter to wait for a predefined number of clock cycles. The core then performs a 4-beat, incrementing, read burst from a parameterized base source address into the register bank. When the burst is complete, the bus master waits for further predefined time, before writing data from the registers as 32 single byte transfers. This data is written, least significant byte first, to a single non-incrementing destination address. This process continues, using the same source and destination addresses, until a power-down or reset condition is reached.

Configurable options

The EBM has a fixed functionality and is not programmable. There are, however, compilation-time or simulation-time options, using Verilog parameters. Table 3.11 lists the configurable options.

Table 3.11. Configurable options



Default value




'1' (True)

When set to 0 (false), this parameter prevents the master from generating any transfers


8-bit vector


Bits [31:24] of the base address for the read burst, dword aligned


8-bit vector


Bits [31:24] of the base address for the write transfers, dword aligned


10-bit vector


The number of IDLE transactions between bursts


The EBM supports little-endian mode only.

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