3.12.1. Bridge designations

The following synchronous AHB-AHB bridges are described in this section:

Ahb2Ahb (1:1)

This is a fully registered bridge for connecting AHB buses that share a common clock. This bridge includes one level of write buffering to enable zero wait-state write transfers across it. Figure 3.19 shows the Ahb2Ahb bridge.

Figure 3.19. Ahb2Ahb bridge

Ahb2AhbSyncDn (N:1)

This bridge connects buses running at different, synchronous frequencies, where clocks share concurrent edges, and where the master is clocked at the same or a higher frequency than the slave.

Figure 3.20 shows the Ahb2AhbSyncDn bridge.

Figure 3.20. Ahb2AhbSyncDn bridge

Ahb2AhbSyncUp (1:N)

This bridge connects buses running at different, synchronous frequencies, where clocks share concurrent edges, and where the master is clocked at the same or a lower frequency than the slave. Figure 3.21 shows the Ahb2AhbSyncUp bridge.

Figure 3.21. Ahb2AhbSyncUp bridge

Trial synthesis of the Ahb2Ahb, Ahb2AhbSyncUp, and Ahb2AhbSyncDn bridges is targeted at a clock period of 6ns, implying a frequency of ~166MHz. The required input and output port constraints are set as follows:

Inputs

Maximum setup time of 30% of clock cycle, implying 1.8ns.

Outputs

Maximum output valid delay of 40% of clock cycle, implying 2.4ns.

Note

These are the preferred synthesis targets, that are not always achievable depending on the technology library used. Trial synthesis using the TSMC 0.13 library has shown that all internal, register-to-register, paths meet the 166MHz target, but that constraints on some ports might have to be relaxed.

Ahb2AhbPass (1:1)

This is a simple combinatorial bridge that connects AHB buses without incurring a latency penalty. You can use this bridge as a latency-free pin-compatible alternative to the other bridges or where a slave gasket, such as the downsizer, is required to connect to a multi-master bus. Figure 3.22 shows the Ahb2AhbPass bridge.

Figure 3.22. Ahb2AhbPass bridge

Trial synthesis of the Ahb2AhbPass bridge is targeted at a clock period of 6ns, implying a frequency of approximately 166MHz. Because of the presence of combinatorial paths through the design, the timing constraints are set as follows:

Input to register

30% of clock cycle, implying 1.8ns.

Register to output

30% of clock cycle, implying 1.8ns.

Input to output

15% of clock cycle, implying 0.9ns.

These are the preferred synthesis targets, that are not always achievable depending on the technology library used. Trial synthesis using the TSMC 0.13 library has shown that all internal, register-to-register, paths meet the 166MHz target, but that constraints on some ports might have to be relaxed.

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