3.12.3. Programmer's model

The general concept of the bridge is described in the following sections:


The scope of memory-map visibility is user-defined.

Preserved address map

Figure 3.24 shows the memory maps for a system with one-to-one address mapping. It is assumed that full visibility of the slaves in system 2 is required.

Figure 3.24. System memory maps without address aliasing

Aliased or piecewise address map

Address-aliasing is a function of the address decoder and of masking-off the high-order address bits in hardware. It is recommended that this is implemented in AHB system 1. Figure 3.25 shows a generalized scheme.

Figure 3.25. Address-aliasing hardware

Figure 3.26 and Figure 3.27 show the use of address-aliasing to make memory in system 2 appear both at address 0 and also at a higher address, so that it can be accessed by system 1 through the bridge. In this design, only the area of ROM is visible through the bridge.

Figure 3.26. System memory maps with aliased addressing

Figure 3.27. System memory maps with piecewise addressing


This section describes the functionality of the synchronous AHB-AHB bridges.


It is recommended that the buses on either side of the bridge are reset together, for at least three cycles of each HCLK. However, AHB2 can be held in reset while AHB1 is free-running, if no transaction is directed at the bridge. You can use this to reduce power consumption on AHB2 while it is unused.

Slave responses

SPLIT and RETRY responses from remote slaves are supported, but they are not propagated back to the master. The bridge inserts wait states on bus 1 using HREADY to hold up the master until the remote slave is ready to complete the outstanding transfer. The bridge slave interface does not generate SPLIT or RETRY responses.


ERROR responses from remote slaves are normally propagated back to the master to determine further action for that transfer. In the Ahb2Ahb bridge (1:1), this response is suppressed for buffered writes because of a transfer correlation issue. For buffered transfers, the master cannot determine exactly when the transfer completes at the slave. If a confirmation of completion is required, a single read can be directed at a remote slave that only completes when any previously buffered writes are also complete.

Wait states

It is an AHB recommendation that slaves must not generate more than 16 wait-states. This is included to help with system latency predictions. However, when using an AHB-AHB bridge, the effects of registered paths, crossing clock domains, slave wait-states, RETRY/SPLIT responses, and bus arbitration have a cumulative effect on the number of wait-states generated by the bridge slave. This implies that the bridge can easily generate wait periods that are greater than 16 cycles in length.

Locked transfers

The bridges are designed so that HMASTLOCK is asserted on AHB2 when the first locked transfer is directed at the bridge. The lock on AHB2 is then held until the entire locked sequence completes on AHB1, even if it contains transfers not directed at the bridge. This ensures coherency of both buses during the locked sequence.

Bidirectional bridging

All AHB-AHB bridges are unidirectional in nature, but you can use them as a pair to form a bidirectional bridge between buses if the following potential deadlock situation is avoided:

  • If both bridges are active simultaneously, that is, a master is accessing a slave across the bridge, then deadlock can occur while both bridges are waiting to be granted the remote bus.

Figure 3.28 shows bidirectional bridging. If M0 accesses S3 through bridge 1 while M3 accesses S0 through bridge 2, the bridge masters, M1, M2, are not granted the bus because the masters M0 and M3 have bus control until their transfers complete.

Figure 3.28. Bidirectional bridging

Deadlock can also happen if one bridge master happens to direct a transfer at the other bridge slave, for example:

M0 → S1/M1 → S2/M2 → S0.

One way to avoid deadlock is to use multi-layer bus matrix on one or both of the AHB buses. The decode must be chosen so that a bridge loop is not possible. Using multi-layer bus matrix on AHB1 for example, enables the transfer M2 → S0 to complete before the transfer M0 → S1, and the deadlock situation is avoided.

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