3.12.4. Optional additional blocks

The following blocks are described in this section:

Error cancel

When an AHB master receives an ERROR response from a slave, it can optionally cancel any pending transfer, while HREADY is LOW, by driving HTRANS to IDLE during the second cycle of the ERROR response. Figure 3.29 shows this.

Figure 3.29. Error cancel timing

Because a registered bridge, except Ahb2AhbPass, cannot predict what the master will do, it must always exhibit either a cancel or continue behavior. Because most AHB masters continue with a pending transfer, the bridge also does this by default. Therefore, if a master that can potentially cancel a transfer on ERROR response is permitted to use the bridge, the ErrorCanc block is required to change the bridge behavior.

When an ERROR response is received by the bridge master, the ErrorCanc logic immediately cancels any pending transfer and the ERROR response is passed back to the originating master. If the master continues with a pending transfer and completes the burst, the ErrorCanc block suppresses the transfer and responds with an ERROR response to each transfer remaining in the burst. Figure 3.30 shows this.

Figure 3.30. Error cancel using ErrorCanc timing


For buffered write transfers, Ahb2Ahb bridge only, slave responses cannot be passed back to the master. The error-cancelling functionality is therefore disabled for buffered transfers in the Ahb2Ahb bridge. To facilitate this, the ErrorCanc logic is integrated into the top level of the Ahb2Ahb bridge.


An AHB master can only abort a burst if it receives an ERROR response or is degranted before the burst is complete. If a master on AHB1, accessing a peripheral through the bridge is degranted before the burst is complete, the bridge master on AHB2 appears to have illegally aborted the burst. Therefore, if the arbiter on AHB1 has the potential to rearbitrate before a burst is complete, to avoid breaking protocol, the bridge must not generate fixed-length bursts. To avoid this, the IncrOverride block must be used. This block overrides HBURSTM to always be INCR.


Under certain circumstances, the ADK arbiter and ADK v1 revisions of the Bus Matrix arbiter might rearbitrate in mid-burst. If either of these are used, the IncrOverride block must be used with the bridges.

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