3.12.5. Signal descriptions

Table 3.12 lists the interface signals for the synchronous AHB-AHB bridge.

Table 3.12. Synchronous AHB-AHB bridge interface signals

Signal

AHB bus

Direction

Description

HADDRM[31:0]

2

Output

The 32-bit system address bus.

HADDRS[31:0]

1

Input

The 32-bit system address bus.

HBURSTM[2:0]

2

Output

Indicates if the transfer forms part of a burst. The bridge supports all types of transfer, that is single, incrementing, or wrapping.

HBURSTS[2:0]

1

Input

Indicates if the transfer forms part of a burst. The bridge supports all types of transfer, that is single, incrementing, or wrapping.

HBUSREQM

2

Output

A signal from the bridge to the arbiter, that indicates that the master interface requires bus 2. There is an HBUSREQ signal for each bus master in the system.

HCLKEN

-

Input

This signal describes the relationship between HCLKS and HCLKM. This is HIGH for coincident edges between clocks.

HCLKM

2

Input

This clock times all bus transfers on AHB2. All signal timings on AHB2 are related to the rising edge of HCLKM.

HCLKS

1

Input

This clock times all bus transfers on AHB1. All signal timings on AHB1 are related to the rising edge of HCLKS.

HGRANTM

2

Input

This signal indicates that the bridge is currently the highest priority master. Ownership of the address and control signals changes at the end of a transfer when HREADYM is HIGH, so the master gets access to the bus when both HREADYM and HGRANTM are HIGH.

HLOCKM

2

Output

When HIGH, this signal indicates that the master requires locked access on bus 2 and no other master must be granted that bus until this signal is LOW.

HMASTLOCKS

1

Input

When HIGH, this signal indicates that the master on bus 1 requires locked access through the bridge and no other master must be granted the bus until this signal is LOW.

HPROTM[3:0]

2

Output

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection.

HPROTS[3:0]

1

Input

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection.

HRDATAM

2

Input

The read data bus, 32 or 64-bit, transfers data from the slave(s) on bus 2, to the bridge, during read operations.

HRDATAS

1

Output

The read data bus, 32 or 64-bit, transfers data from the bridge to the bus master during a read operation.

HREADYM

2

Input

When HIGH, the HREADYM signal indicates that a transfer has finished on bus 2. This signal can be driven LOW by a slave to extend a transfer.

HREADYOUTS

1

Output

When HIGH, the HREADYOUTS signal indicates that a transfer has finished on bus 1. This signal can be driven LOW by the bridge to extend a transfer.

HREADYS

1

Input

Input version of HREADYOUTS, required by the slave interface.

HRESETn

-

Input

This signal is active LOW and resets the system and the bus.

HRESPM[1:0]

2

Input

The transfer response provides additional information on the status of a transfer. Four different responses are supported, OKAY, ERROR, RETRY, and SPLIT.

HRESPS[1:0]

1

Output

The transfer response provides additional information on the status of a transfer. Only two responses are supported on the slave interface, OKAY and ERROR.

HSELS

1

Input

The bridge slave interface uses the HSELS signal to determine when it must respond to a bus transfer.

HSIZEM[2:0]

2

Output

Indicates the size of the transfer. The bridge uses 32-bit data for read and write transfers.

HSIZES[2:0]

1

Input

Indicates the size of the transfer. The bridge uses 32-bit data for read and write transfers.

HTRANSM[1:0]

2

Output

Indicates the type of the current transfer, and can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HTRANSS[1:0]

1

Input

Indicates the type of the current transfer, and can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HWDATAM

2

Output

The write data bus, 32 or 64-bit, transfers data from the bridge to the slave(s) on bus 2, during write operations.

HWDATAS

1

Input

The write data bus, 32 or 64-bit, transfers data from the bus master to the bridge during a write operation.

HWRITEM

2

Output

When HIGH, this signal indicates a write transfer, and when LOW, a read transfer.

HWRITES

1

Input

When HIGH, this signal indicates a write transfer, and when LOW, a read transfer.

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