3.13.1. Programmer's model

The following sections describe the programming and operation of the asynchronous AHB-AHB bridge:


The bridge has two asynchronous reset domains, HRESETSn and HRESETMn. Each reset must be asserted for at least one cycle of the relevant clock. No transfer must be attempted through the bridge until both sides have exited from reset.

Low power operation

For low power operation, you can stop the clock on AHB2 or hold it in reset while keeping AHB1 active, if any current bridge transfer has completed and the bridge is not addressed while AHB2 is inactive.

Slave responses

Slave responses of SPLIT or RETRY are serviced locally in the appropriate way. The transfer is driven back onto the bus while AHB1 is stalled. The behavior of the master to an ERROR response is undefined, so the error is passed across the bridge to the originating master, and can either continue or abort the current burst.

Locked transfers

If the bridge is accessed with a locked transfer, that is, HMASTLOCKS is HIGH, it locks the transfer onto AHB2, using HLOCKM.


For a succession of locked transfers on AHB1, the bridge keeps AHB2 locked by keeping HLOCKM asserted for the IDLE transfers between NONSEQ transactions, even if not directed at the bridge. HLOCKM remains asserted after a locked transfer, until the next unlocked transfer has propagated across the bridge.

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