3.13.2. Signal descriptions

Table 3.13 lists the interface signals for the asynchronous AHB-AHB bridge.

Table 3.13. Asynchronous AHB-AHB bridge interface signals

Signal

Block

Clock domain

Direction

Description

HADDRM[31:0]

Master interface

Master

Output

The 32-bit system address bus.

HADDRS[31:0]

Slave interface

Slave

Input

The 32-bit system address bus.

HBURSTM[2:0]

Master interface

Master

Output

Indicates if the transfer forms part of a burst. The bridge only generates transfers of type SINGLE.

HBURSTS[2:0]

Slave interface

Slave

Input

Indicates if the transfer forms part of a burst. The bridge supports all types of transfer, that is single, incrementing, or wrapping.

HBUSREQM

Master interface

Master

Output

A signal from the bridge to the arbiter, that indicates that the master interface requires bus 2.

HCLKM

Master interface

-

Input

This clock times all bus transfers. All signal timings on the AHB2 are related to the rising edge of HCLKM.

HCLKS

Slave interface

-

Input

This clock times all bus transfers. All signal timings on AHB1 are related to the rising edge of HCLKS.

HGRANTM

Master interface

Master

Input

This signal indicates that the bridge is currently the highest priority master. Ownership of the address and control signals changes at the end of a transfer when HREADYM is HIGH, so the master gets access to the bus when both HREADYM and HGRANTM are HIGH.

HLOCKM

Master interface

Master

Output

When HIGH, this signal indicates that the master requires locked access on bus 2.

HMASTLOCKS

Slave interface

Slave

Input

When HIGH, this signal indicates that the master on bus 1 requires locked access through the bridge.

HPROTM[3:0]

Master interface

Master

Output

The protection control signals provide additional information about a bus access and are passed across the bridge.

HPROTS[3:0]

Slave interface

Slave

Input

The protection control signals provide additional information about a bus.

HRDATAM[31:0]

Master interface

Master

Input

The 32-bit read data bus transfers data from the slave(s) on bus 2, to the bridge, during read operations.

HRDATAS[31:0]

Slave interface

Slave

Output

The 32-bit read data bus transfers data from the bridge to the bus master during a read operation.

HREADYM

Master interface

Master

Input

When HIGH, the HREADYM signal indicates that a transfer has finished on bus 2. This signal can be driven LOW by a slave to extend a transfer.

HREADYOUTS

Slave interface

Slave

Output

When HIGH, the HREADYOUTS signal indicates that a transfer has finished on bus 1. This signal can be driven LOW by the bridge to extend a transfer.

HREADYS

Slave interface

Slave

Input

Multiplexed HREADYOUT signals to indicate when transfer is complete on AHB1.

HRESETMn

Master interface

Master

Input

This signal is active LOW and resets AHB2.

HRESETSn

Slave interface

Slave

Input

This signal is active LOW and resets AHB1.

HRESPM[1:0]

Master interface

Master

Input

The transfer response provides additional information on the status of a transfer. Four different responses are supported, OKAY, ERROR, RETRY, and SPLIT.

HRESPS[1:0]

Slave interface

Slave

Output

The transfer response provides additional information on the status of a transfer.

HSELS

Slave interface

Slave

Input

The bridge slave interface uses the HSELS signal to determine when it must respond to a bus transfer.

HSIZEM[M:0]

Master interface

Master

Output

Indicates the size of the transfer. The bridge supports sizes up to 32-bit.

HSIZES[2:0]

Slave interface

Slave

Input

Indicates the size of the transfer. The bridge supports sizes up to 32-bit.

HTRANSM[1:0]

Master interface

Master

Output

Indicates the type of the current transfer. The bridge supports transfers of type IDLE or NONSEQ.

HTRANSS[1:0]

Slave interface

Slave

Input

Indicates the type of the current transfer, and can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HWDATAM[31:0]

Master interface

Master

Output

The 32-bit write data bus transfers data from the bridge to the slave(s) on bus 2, during write operations.

HWDATAS[31:0]

Slave interface

Slave

Input

The 32-bit write data bus transfers data from the bus master to the bridge during a write operation.

HWRITEM

Master interface

Master

Output

When HIGH, this signal indicates a write transfer, and when LOW, a read transfer.

HWRITES

Slave interface

Slave

Input

When HIGH, this signal indicates a write transfer, and when LOW, a read transfer.

SCANENABLE

Scan

Slave

Input

Scan test mode enable.

SCANINHCLKM

Scan

Master

Input

Scan chain input for HCLKM registers.

SCANINHCLKS

Scan

Slave

Input

Scan chain input for HCLKS registers.

SCANOUTHCLKM

Scan

Master

Output

Scan chain output for HCLKM registers.

SCANOUTHCLKS

Scan

Slave

Output

Scan chain output for HCLKS registers.

Copyright © 2003, 2007 ARM Limited. All rights reserved.ARM DDI 0243C
Non-Confidential