3.15.1. Programmer’s model

Table 3.14 lists how, by convention, the IRQ interrupt bits [5:1] must be used. Bit 0 and bit 6 upwards are available for use as required. For the FIQ interrupt, the bits can be used as required.

Table 3.14. Interrupt standard configuration

Bit

Interrupt source

1

Software interrupt

2

Comms Rx

3

Comms Tx

4

Timer 1

5

Timer 2

The software can control the source interrupt lines to generate software interrupts. These interrupts are generated before interrupt masking, in the same way as external source interrupts. Software interrupts are cleared by writing to the software interrupt clear register, ICSoftIntClear. See Software Interrupt Clear Register. This is normally done at the end of the interrupt service routine.

Interrupt flow sequence

The following procedure shows the sequence for the vectored interrupt flow:

  1. An interrupt occurs.

  2. The ARM processor branches to either the IRQ or FIQ exception vector.

  3. If the interrupt is an IRQ, read the ICVectAddr register and branch to the interrupt service routine. This can be done using an LDR PC instruction. Reading the ICVectorAddr register updates the interrupt controllers hardware priority register.

  4. Stack the workspace so that IRQ interrupts can be re-enabled.

  5. Enable the IRQ interrupts so that a higher priority can be serviced.

  6. Execute the Interrupt Service Routine (ISR).

  7. Clear the requesting interrupt in the peripheral, or write to the ICSoftIntClear register if the request was generated by a software interrupt.

  8. Disable the interrupts and restore the workspace.

  9. Write to the ICVectAddr register. This clears the respective interrupt in the internal interrupt priority hardware.

  10. Return from the interrupt. This re-enables the interrupts.

Simple interrupt flow

The following procedure shows how you can use the interrupt controller without using vectored interrupts or the interrupt priority hardware. For example, you can use it for debugging.

  1. An interrupt occurs.

  2. Branch to IRQ or FIQ exception vector.

  3. Branch to the interrupt handler.

  4. Interrogate the ICIRQStatus register to determine the source that generated the interrupt, and prioritize the interrupts if there are multiple active interrupt sources. This takes a number of instructions to compute.

  5. Branch to the correct ISR.

  6. Execute the ISR.

  7. Clear the interrupt. If the request was generated by a software interrupt, the ICSoftIntClear register must be written to.

  8. Check the ICIRQStatus register to ensure that no other interrupt is active. If there is an active request go to Step 4.

  9. Return from the interrupt.

Note

If the above flow is used, you must not read or write to the ICVectorAddr register.

To ensure that the vector address register can be read in a single instruction, the IC base address must be 0xFFFFF000, the upper 4K of memory. See Vector Address Register. Placing the IC anywhere else in memory increases interrupt latency as the ARM processor is unable to access the ICVectorAddr register using a single instruction. The offset of any particular register from the base address is fixed.

Table 3.15 lists the registers in base offset order.

Table 3.15. Interrupt controller registers

Name

Base offset

Type

Width

Reset value

Description

ICIRQSTATUS

0x000

Read

32

0x00000000

See IRQ Status Register

ICFIQSTATUS

0x004

Read

32

0x00000000

See FIQ Status Register

ICRAWINTR

0x008

Read

32

-

See Raw Interrupt Status Register

ICINTSELECT

0x00C

Read/ write

32

0x00000000

See Interrupt Select Register

ICINTENABLE

0x010

Read/ write

32

0x00000000

See Interrupt Enable Register

ICINTENCLEAR

0x014

Write

32

-

See Interrupt Enable Clear Register

ICSOFTINT

0x018

Read/ write

32

0x00000000

See Software Interrupt Register

ICSOFTINTCLEAR

0x01C

Write

32

-

See Software Interrupt Clear Register

ICPROTECTION

0x020

Read/ write

1

0x0

See Protection Enable Register

ICVECTADDR

0x030

Read/ write

32

0x00000000

See Vector Address Register

ICDEFVECTADDR

I0x034

Read/ write

32

0x00000000

See Default Vector Address Register

ICITCR

0x300

Read/ write

1

-

See Test Control Register

ICITIP1

I0x304

Read

2

-

See Test Input Register 1

ICITIP2

0x308

Read

32

-

See Test Input Register 2

ICITOP1

0x30C

Read

2

0x0

See Test Output Register 1

ICITOP2

0x310

Read

32

0x00000000

See Test Output Register 2

ICPERIPHID0

0xFE0

Read

8

0x08

See Peripheral Identification Registers

ICPERIPHID1

0xFE4

Read

8

0x18

See Peripheral Identification Registers

ICPERIPHID2

0xFE8

Read

8

0x04

See Peripheral Identification Registers

ICPERIPHID3

0xFEC

Read

8

0x00

See Peripheral Identification Registers

ICPCELLID0

0xFF0

Read

8

0x0D

See PrimeCell Identification Registers

ICPCELLID1

0xFF4

Read

8

0xF0

See PrimeCell Identification Registers

ICPCELLID2

0xFF8

Read

8

0x05

See PrimeCell Identification Registers

ICPCELLID3

0xFFC

Read

8

0xB1

See PrimeCell Identification Registers

IRQ Status Register

The ICIRQSTATUS register is read-only. It provides the status of interrupts [31:0] after IRQ masking. Table 3.16 lists the register bit assignments.

Table 3.16. ICIRQSTATUS Register bit assignments

Bits

Name

Function

[31:0]

IRQStatus

Shows the status of the interrupts after masking by the ICIntEnable and ICIntSelect registers. A HIGH bit indicates that the interrupt is active, and generates an interrupt to the processor.

FIQ Status Register

The ICFIQSTATUS register is read-only. It provides the status of the interrupts after FIQ masking. Table 3.17 lists the register bit assignments.

Table 3.17. ICFIQSTATUS Register bit assignments

Bits

Name

Function

[31:0]

FIQStatus

Shows the status of the interrupts after masking by the ICIntEnable and ICIntSelect registers. A HIGH bit indicates that the interrupt is active, and generates an interrupt to the processor.

Raw Interrupt Status Register

The ICRAWINTR register is read-only. It provides the status of the source interrupts, and software interrupts, to the interrupt controller. Table 3.18 lists the register bit assignments.

Table 3.18. ICRAWINTR Register bit assignments

Bits

Name

Function

[31:0]

RawInterrupt

Shows the status of the interrupts before masking by the enable registers. A HIGH bit indicates that the appropriate interrupt request is active before masking.

Interrupt Select Register

The ICINTSELECT register is read/write. It selects whether the corresponding interrupt source generates an FIQ or an IRQ interrupt. Table 3.19 lists the register bit assignments.

Table 3.19. ICINTSELECT Register bit assignments

Bits

Name

Function

[31:0]

IntSelect

Selects type of interrupt for interrupt request:

0 = IRQ interrupt

1 = FIQ interrupt.

Interrupt Enable Register

The ICINTENABLE register is read/write. It enables the interrupt request lines, by masking the interrupt sources for the IRQ interrupt. Table 3.20 lists the register bit assignments.

Table 3.20. ICINTENABLE Register bit assignments

Bits

Name

Function

[31:0]

IntEnable

Enables the interrupt request lines:

0 = Interrupt disabled.

1 = Interrupt enabled. Enables interrupt request to processor.

On reset, all interrupts are disabled. A HIGH bit sets the corresponding bit in the ICIntEnable register. A LOW bit has no effect.

Interrupt Enable Clear Register

The ICINTENCLEAR register is write-only. It clears bits in the ICIntEnable register. Table 3.21 lists the register bit assignments.

Table 3.21. ICINTENCLEAR Register bit assignments

Bits

Name

Function

[31:0]

IntEnable Clear

Clears bits in the ICIntEnable register.

A HIGH bit clears the corresponding bit in the ICIntEnable register. A LOW bit has no effect.

Software Interrupt Register

The ICSOFTINT register is read/write. It generates software interrupts. Table 3.22 lists the register bit assignments.

Table 3.22. ICSOFTINT Register bit assignments

Bits

Name

Function

[31:0]

SoftInt

Setting a bit generates a software interrupt for the specific source interrupt before interrupt masking.

A HIGH bit sets the corresponding bit in the ICSoftInt register. A LOW bit has no effect.

Software Interrupt Clear Register

The ICSOFTINTCLEAR register is write-only. It clears bits in the ICSoftInt register. Table 3.23 lists the register bit assignments.

Table 3.23. ICSOFTINTCLEAR Register bit assignments

Bits

Name

Function

[31:0]

SoftIntClear

Clears bits in the ICSoftInt register.

A HIGH bit clears the corresponding bit in the ICSoftInt register. A LOW bit has no effect.

Protection Enable Register

The ICPROTECTION register is read/write. It enables or disables protected register access. Figure 3.34 shows the register bit assignments.

Figure 3.34. ICPROTECTION Register bit assignments

Table 3.24 lists the register bit assignments.

Table 3.24. ICPROTECTION Register bit assignments

Bits

Name

Function

[31:1]

Reserved

-

[0]

Protection

Enables or disables protected register access.

When enabled, only privileged mode accesses, reads and writes, can access the interrupt controller registers.

When disabled, both User mode and privileged mode can access the registers.

This register is cleared on reset, and can only be accessed in privileged mode.

Note

If the bus master cannot generate accurate protection information, leave this register in its reset state to enable User mode access.

Vector Address Register

The ICVECTADDR register is read/write. It contains the Interrupt Service Routine (ISR) address of the currently active interrupt. Table 3.25 lists the register bit assignments.

Table 3.25. ICVECTADDR Register bit assignments

Bits

Name

Function

[31:0]

VectorAddr

Contains the address of the currently active ISR. Any writes to this register clear the interrupt.

Reading from this register provides the address of the ISR, and indicates to the priority hardware that the interrupt is being serviced. Writing to this register indicates to the priority hardware that the interrupt has been serviced. You must use the register as follows:

  • the ISR reads the ICVectAddr register when an IRQ interrupt is generated

  • at the end of the ISR, the ICVectAddr register is written to, to update the priority hardware.

Reading or writing to the register at other times can cause incorrect operation.

Default Vector Address Register

The ICDEFVECTADDR register is read/write. It contains the default ISR address. Table 3.26 lists the register bit assignments.

Table 3.26. ICDEFVECTADDR Register bit assignments

Bits

Name

Function

[31:0]

Default VectorAddr

Contains the address of the default ISR handler

Test Control Register

The ICITCR register is read/write. It selects test mode, and is cleared on reset. Figure 3.35 shows the register bit assignments.

Figure 3.35. ICITCR Register bit assignments

Table 3.27 lists the register bit assignments.

Table 3.27. ICITCR Register bit assignments

Bits

Name

Function

[31:1]

Reserved

-

[0]

ITEN

Selects test mode, to use ICITIP test registers in place of input signals

Test Input Register 1

The ICITIP1 register is read-only. It indicates the status of the nICIRQIN and nICFIQIN daisy chain input lines. Figure 3.36 shows the register bit assignments.

Figure 3.36. ICITIP1 Register bit assignments

Table 3.28 lists the register bit assignments.

Table 3.28. ICITIP1 Register bit assignments

Bits

Name

Function

[31:8]

Reserved

-

[7]

I

Indicates status of nICIRQIN when ICITCR register is LOW

[6]

F

Indicates status of nICFIQIN when ICITCR register is LOW

[5:0]

Reserved

-

Test Input Register 2

The ICITIP2 register is read-only. It indicates the status of the ICVECTADDRIN daisy chain input lines. Table 3.29 lists the register bit assignments.

Table 3.29. ICITIP2 Register bit assignments

Bits

Name

Function

[31:0]

VectorAddrIn

Indicates status of ICVECTADDRIN when ICITCR register is LOW

Test Output Register 1

The ICITOP1 register is read-only. It indicates the status of the nICIRQ and nICFIQ interrupt request lines to the processor. Figure 3.37 shows the register bit assignments.

Figure 3.37. ICITOP1 Register bit assignments

Table 3.30 lists the bit assignments for the ICITOP1 register.

Table 3.30. ICITOP1 Register bit assignments

Bits

Name

Function

[31:8]

Reserved

-

[7]

I

Status of nICIRQ interrupt line. If set HIGH, the interrupt request is active

[6]

F

Status of nICFIQ interrupt line. If set HIGH, the interrupt request is active

[5:0]

Reserved

-

Test Output Register 2

The ICITOP2 register is read-only. It indicates the status of the ICVECTADDROUT lines from the interrupt controller. Table 3.31 lists the register bit assignments.

Table 3.31. ICITOP2 Register bit assignments

Bits

Name

Function

[31:0]

VectorAddrOut

Indicates status of ICVECTADDROUT from interrupt controller

Peripheral Identification Registers

The ICPERIPHID0-3 registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options of the peripheral:

Part number [11:0]

This identifies the peripheral. The three digit product code 0x90 is used for the interrupt controller.

Designer [19:12]

This is the identification of the designer. ARM Ltd is 0x41 (ASCII A).

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.38 shows the register bit assignments.

Figure 3.38. ICPERIPHID0-3 Register bit assignments

The four 8-bit peripheral identification registers are described in the following sections:

Peripheral Identification Register 0

The ICPERIPHID0 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.32 lists the register bit assignments.

Table 3.32. ICPERIPHID0 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:0]

Partnumber0

These bits read back as 0x90

Peripheral Identification Register 1

The ICPERIPHID1 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.33 lists the register bit assignments.

Table 3.33. ICPERIPHID1 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:4]

Designer0

These bits read back as 0x1

[3:0]

Partnumber1

These bits read back as 0x1

Peripheral Identification Register 2

The ICPERIPHID2 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.34 lists the register bit assignments.

Table 3.34. ICPERIPHID2 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:4]

Revision

These bits read back as 0x0

[3:0]

Designer1

These bits read back as 0x4

Peripheral Identification Register 3

The ICPERIPHID3 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.35 lists the register bit assignments.

Table 3.35. ICPERIPHID3 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:0]

Configuration

These bits read back as 0x0

PrimeCell Identification Registers

The ICPCELLID0-3 registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. The read-only register can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system. Figure 3.39 shows the register bit assignments.

Figure 3.39. ICPCELLID0-3 Register bit assignments

The four 8-bit registers are described in the following subsections:

PrimeCell Identification Register 0

The ICPCELLID0 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.36 lists the register bit assignments.

Table 3.36. ICPCELLID0 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:0]

ICPCellID0

These bits read back as 0x0D

PrimeCell Identification Register 1

The ICPCELLID1 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.37 lists the register bit assignments.

Table 3.37. ICPCELLID1 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:0]

ICPCellID1

These bits read back as 0xF0

PrimeCell Identification Register 2

The ICPCELLID2 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.38 lists the register bit assignments.

Table 3.38. ICPCELLID2 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:0]

ICPCellID2

These bits read back as 0x05

PrimeCell Identification Register 3

The ICPCELLID3 register is read-only. It is hard-coded and the fields within the register determine the reset value. Table 3.39 lists the register bit assignments.

Table 3.39. ICPCELLID3 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must be written as zeros

[7:0]

ICPCellID3

These bits read back as 0xB1

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