3.16.1. Programmer's model

Programming details for the downsizer are described in the following sections:

Downsizer transfers

The following are options for downsizer transfers:

Downsizer not selected

When the HSELS signal of the downsizer module is LOW, the transfer is passed to the 32-bit AHB and HSELM is driven LOW. The 32-bit slaves must ignore the transfers by monitoring HSELM and HADDRM. HREADYS from the 64-bit bus is output to HREADYM. All 32-bit devices connected to the 32-bit AHB must monitor this HREADYM signal to determine the end of the current transfer and the start of the next.

Narrow transfers, downsizer selected

If the downsizer module is selected, and the transfer is 32 bits or less, the downsizer module passes the transfer through. All of the control signals and responses from the slave are left unmodified. In this case, the only function of the downsizer is to route the appropriate half of the wide master write data bus on to the narrow slave data bus for write transfers.

Read transfers require even less control and the narrow slave read data is replicated across the wide master bus.

Table 3.41 shows the handling of narrow transfers.

Table 3.41. Narrow transfer handling

Transfer on 64-bit AHB

Transfer on 32-bit AHB

Address

32, 16, or 8-bit transfer

32, 16, or 8-bit transfer

HADDR pass through.

If HADDR[2] = 0 then HWDATAS[31:0] pass through else HWDATAS[63:32] pass through. HRDATAS = HRDATAM, HRDATAM.

For 32, 16, and 8-bit transfers, HWDATA is selected by bit [2] of the transfer address. If this bit is set to 0, HWDATA[31:0] is routed to the 32-bit AHB. If this bit is set to 1, bits [63:32] are routed.

If an ERROR, SPLIT, or RETRY response is received from the 32-bit slave, the downsizer module automatically terminates the current transfer by passing the response to the 64-bit bus. If the current transfer request on the 64-bit bus is a valid transfer (NON_SEQ or SEQ), it is captured by the registers in the downsizer module and is applied to the 32-bit AHB one cycle later. The downsizer module inserts a wait state on the 64-bit bus to ensure the next transfer is not missed.

If the transfer is a burst and an ERROR response is received from a 32-bit slave, the rest of the burst is blocked. This behavior is generated by the error-blocking logic and can be removed from the code if necessary.

Wide transfers, downsizer selected

The role of the downsizer module is more involved for 64-bit transfers. For both read and write transfers, the wide master transfers are broken down into two narrow slave cycles. The address going to the slave is modified, to ensure that the two slave accesses go to different address locations. Table 3.42 shows the address line modification and data routing.

Table 3.42. Address line modification and data routing

Transfer on 64-bit AHB

Transfer on 32-bit AHB

Address

64-bit transfer

Cycle 1

HADDR pass through.

HWDATAS[31:0] pass through.

HRDATAM stored in downsizer module.

HADDRS[2:0] must equal 000.

Cycle 2

HADDRM[2] set to 1.

HWDATAS[63:32] pass through.

HRDATAM pass through to HRDATAS[63:32].

Previous stored data output to HRDATAS[31:0].

64-bit write transfers are split into two 32-bit transfers on two successive addresses. Table 3.42 lists the generation of HADDRM[2] and the routing of data write. Because HWDATAS is stable during the two AHB transfers on the 32-bit AHB, no register is required to hold HWDATA.

During 64-bit read accesses, the construction of a full-width word for the master to read two slave accesses is required. The data from the first read is latched, and the data from the second read flows straight through the block. Bits [31:0] are always transferred in the first cycle, and bits [63:32] are transferred in the second cycle using the next word address. This transfer characteristic occurs independently of target system endianness.

If an ERROR, SPLIT, or RETRY response is received from the 32-bit slave, the response is passed to the 64-bit bus without delay. If this happens on the first half of the 64-bit transfer, the second half of the transfer is not carried out.

If a two-cycle response is received, the downsizer module automatically aborts the current transfer by inserting an IDLE cycle on the 32-bit bus. If the current transfer request on the 64-bit bus is a valid transfer, NON_SEQ or SEQ, it is captured by the registers in the downsizer module and is applied to the 32-bit AHB one cycle later. The downsizer module inserts a wait state on the 64-bit bus to ensure the next transfer is not missed.

If the transfer is a burst and an ERROR response is received from 32-bit slave, the rest of the burst is blocked.

Unsupported transfers

The following transfer types are not supported by the downsizer module:

Wide transfers

If the downsizer module receives a transfer request greater than 64 bits wide, with HSELS = 1, the response is undefined.

Unaligned transfers

Unaligned transfers are not supported.

Burst blocking after error

If an ERROR response is received from a 32-bit slave during a 64-bit burst, and if the 64-bit master continues the burst, the rest of the burst is blocked. During blocking, the ERROR response is fed back to the 64-bit AHB and an IDLE transfer is issued to the 32-bit AHB. The blocking ends when a nonsequential transfer request is detected, or if HSELS on the downsizer module is LOW. This feature ensures that there is no discontinuity in HADDR and HTRANS.

The blocking does not apply to 32,16, or 8-bit transfers. In these cases, the rest of the transfer requests pass through as normal. If a busy cycle is detected during burst blocking, the downsizer module replies with an OKAY response. However, the subsequent sequential transfers are still blocked.

If the ERROR response occurs in the last cycle of the burst, no blocking is generated because the next transfer is an IDLE or nonsequential access. In this case, if the next access is nonsequential, the downsizer module issues an IDLE cycle on the 32-bit AHB in the second cycle of the ERROR response, stores the transfer control information, and applies it to the 32-bit AHB in the following cycle.

A wait state is inserted on the 64-bit bus to enable the 32-bit bus to catch up with the transfer.

Slave responses

When a RETRY or SPLIT response is received, an IDLE cycle is issued to the 32-bit AHB in the second cycle of the RETRY or SPLIT response. If the response occurs during the first half of a 64-bit transfer, the second half is not completed. If the 64-bit master continues to output a valid transfer while the downsizer module is still selected, the transfer is stored and applied to the 32-bit AHB a cycle later. A wait state is output to the 64-bit bus to enable the 32-bit AHB to catch up.

In the case of SPLIT or RETRY responses during 64-bit transfers, the HRDATA value received is unpredictable and must be ignored.

Modification of control signals

Table 3.43 lists that, for both read and write transfers, the control signals are modified in the same way.

Table 3.43. Signal mapping when downsizer module is activated

Control signals

Master cycle type

Replaced by slave cycles

Comments

HTRANS

IDLE

to

IDLE

-

BUSY

to

BUSY

-

NONSEQ

to

NONSEQ, followed by a SEQ

No change if transfer is 8, 16, or 32-bit.

SEQ

to

SEQ, followed by a SEQ

No change if transfer is 8, 16, or 32-bit.

Exception for WRAP16 boundary, WRAP16 is mapped to INCR and NONSEQ is issued at 32-word boundary.

HADDR[2]

= 0

to

0 then 1

No change if transfer is 8, 16, or 32-bit.

= 1

-

-

Not permitted.

HSIZE

8/16/32 bit

to

8/16/32 bit

No conversion required.

64 bit

to

32 bit

Conversion process activated.

128/256 bit

to

32 bit

Not supported.

HBURST

SINGLE

to

INCR

No change if transfer is 8, 16, or 32-bit.

INCR

to

INCR

No change if transfer is 8, 16, or 32-bit.

INCR4

to

INCR8

No change if transfer is 8, 16, or 32-bit.

WRAP4

to

WRAP8

No change if transfer is 8, 16, or 32-bit.

INCR8

to

INCR16

No change if transfer is 8, 16, or 32-bit.

WRAP8

to

WRAP16

No change if transfer is 8, 16, or 32-bit.

INCR16

to

INCR

No change if transfer is 8, 16, or 32-bit.

WRAP16

to

INCR

No change if transfer is 8, 16, or 32-bit.

NONSEQ broadcast if WRAP boundary is reached.

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