3.17.2. Signal descriptions

The funnel has two AHB ports. The 64-bit AHB port is a slave interface and uses an S suffix. The 32-bit AHB port has an M suffix. Table 3.45 lists the signal connections for the funnel module.

Table 3.45. Funnel interface signals

Signal

Direction

Description

HCLK

Input

System bus clock. Logic is triggered on the clock rising edge.

HRESETn

Input

Activate low asynchronous reset.

Signals connected to 64-bit AHB

HADDR2S

Input

Address bit 2 from 64-bit AHB.

HRDATAS[63:0]

Output

Read data to 64-bit bus.

HREADYS

Input

HREADY signal on the 64-bit AHB bus, indicating start and end of transfer on the 64-bit bus.

HWDATAS[63:0]

Input

Write data from 64-bit bus.

Signals connected to 32-bit AHB

HRDATAM[31:0]

Input

Read data from 32-bit slave.

HWDATAM[31:0]

Output

Write data from 32-bit slave.

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