4.1.1. Programmer’s model

The base address of the remap and pause controller memory is not fixed and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed. Table 4.1 lists the remap and pause controller registers in base offset order.

Table 4.1. Remap and pause register summary

Name

Base

offset

Type

Width

Reset

value

Description

Pause

0x00

WO

-

-

See Pause Register

Remap

0x04

R/W

1

0x0

See Remap Register

ResetStatus

0x08

R/W

8

0x01

See Reset Status Register

ResetStatusClr

0x0C

WO

8

-

See Reset Status Clear Register

RpcPeriphID0

0xFE0

RO

8

0x09

See Peripheral Identification Registers

RpcPeriphID1

0xFE4

RO

8

0x18

See Peripheral Identification Registers

RpcPeriphID2

0xFE8

RO

8

0x04

See Peripheral Identification Registers

RpcPeriphID3

0xFEC

RO

8

0x00

See Peripheral Identification Registers

RpcPCellID0

0xFF0

RO

8

0x0D

See PrimeCell Identification Registers

RpcPCellID1

0xFF4

RO

8

0xF0

See PrimeCell Identification Registers

RpcPCellID2

0xFF8

RO

8

0x05

See PrimeCell Identification Registers

RpcPCellID3

0xFFC

RO

8

0xB1

See PrimeCell Identification Registers

Pause Register

Any write to this location sets the PAUSE Register output HIGH. The exact effect of writing to this location is not defined, but typically this prevents the processor from fetching further instructions until the receipt of an interrupt of a power-on reset.

Remap Register

Bit 0 of the REMAP Register drives the REMAP output. This is typically used to change the memory map from that required during boot-up to that for normal operation. This bit is cleared at reset and, when set, can only be cleared again by resetting the block.

Reset Status Register

The RESETSTATUS Register provides the reset status of the system. Only bit 0 is defined in this specification, and provides the PRESETn status:

  • set HIGH at reset

  • set LOW through the ResetStatusClr register.

Further bits in the RESETSTATUS register can be implemented to provide more detailed reset information. The RESETSTATUS register has a dual mechanism for setting and clearing bits, enabling independent bits to be altered with no knowledge of the other bits in the register. A write to the RESETSTATUS register has the effect of setting all the bits, except bit 0, that have a corresponding HIGH in the write data.

Reset Status Clear Register

The RESETSTATUSCLR Register location clears bits in the RESETSTATUS register. Each HIGH bit in the write data to this location causes the corresponding RESETSTATUS bit to be cleared.

Peripheral Identification Registers

The RPCPERIPHID0-3 registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options for the peripheral:

Part number [11:0]

This identifies the peripheral. The three-digit product code 0x809 is used for the remap and pause controller.

Designer [19:12]

This is the identification of the designer. ARM Limited is 0x41 (ASCII A).

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 4.2 shows the register bit assignments.

Figure 4.2. RPCPERIPHID0-3 Register bit assignment s

Note

When you design a systems memory map you must remember that the register has a 4KB-memory footprint. All memory accesses to the peripheral identification registers must be 32-bit, using the LDR and STR instructions.

The four 8-bit peripheral identification registers are described in the following subsections:

Peripheral Identification Register 0

The RPCPERIPHID0 register is hard-coded and the fields within the register determine the reset value. Table 4.2 lists the register bit assignments.

Table 4.2. RPCPERIPHID0 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined must read as zeros

[7:0]

PartNumber0

These bits read back as 0x09

Peripheral Identification Register 1

The RPCPERIPHID1 register is hard-coded and the fields within the register determine the reset value. Table 4.3 lists the register bit assignments.

Table 4.3. RPCPERIPHID1 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:4]

Designer0

These bits read back as 0x1

[3:0]

PartNumber1

These bits read back as 0x8

Peripheral Identification Register 2

The RPCPERIPHID2 register is hard-coded and the fields within the register determine the reset value. Table 4.4 lists the register bit assignments.

Table 4.4. RPCPERIPHID2 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:4]

Revision

These bits return the peripheral revision

[3:0]

Designer1

These bits read back as 0x4

Peripheral Identification Register 3

The RPCPERIPHID3 register is hard-coded and the fields within the register determine the reset value. Table 4.5 lists the register bit assignments.

Table 4.5. RPCPERIPHID3 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

Configuration

These bits read back as 0x00

PrimeCell Identification Registers

The RPCPCELLID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The RPCPCELLID register is set to 0xB105F00D. Figure 4.3 shows the register bit assignments.

Figure 4.3. RPCPCELLID0-3 Register bit assignments

The four, 8-bit PrimeCell identification registers are described in the following subsections:

PrimeCell Identification Register 0

The RPCPCELLID0 register is hard-coded and the fields within the register determine the reset value. Table 4.6 lists the register bit assignments.

Table 4.6. RPCPCELLID0 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

RpcPCellID0

These bits read back as 0x0D

PrimeCell Identification Register 1

The RPCPCELLID1 register is hard-coded and the fields within the register determine the reset value. Table 4.7 lists the register bit assignments.

Table 4.7. RPCPCELLID1 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

RpcPCellID1

These bits read back as 0xF0

PrimeCell Identification Register 2

The RPCPCELLID2 register is hard-coded and the fields within the register determine the reset value. Table 4.8 lists the register bit assignments.

Table 4.8. RPCPCELLID2 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

RpcPCellID2

These bits read back as 0x05

PrimeCell Identification Register 3

The RPCPCELLID3 register is hard-coded and the fields within the register determine the reset value. Table 4.9 lists the register bit assignments.

Table 4.9. RPCPCELLID3 Register bit assignments

Bits

Name

Description

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

RpcPCellID3

These bits read back as 0xB1

Copyright © 2003, 2007 ARM Limited. All rights reserved.ARM DDI 0243C
Non-Confidential