4.2.1. Programmer’s model

The slave only responds to a transfer when not in reset, PRESETn HIGH, and when PSEL is HIGH and PENABLE is LOW at the time of a rising edge on PCLK. The timing of the slave corresponds to the APB specification.

The functionality of the slave depends on the address location being accessed and the direction of the data. Only bits [11:2] of the address are decoded, and this supports accesses with word-aligned addresses. Because of the partial address decode, the same location is accessible at several addresses. For example, Register 0 is accessible at 0x0000, 0x1000, 0x2000, ..., until the decode range of PSEL from the bridge is exceeded.

Table 4.11 lists the example APB slave memory map.

Table 4.11. Example APB slave memory map

Name

Base

offset

Type

Width

Reset

value

Description

R0

0x00

R/W

32

0x00000000

Read/write data into R0.

R1

0x04

R/W

32

0x00000000

Read/write data into R1.

R2

0x08

R/W

32

0x00000000

Read/write data into R2.

R3

0x0C

R/W

32

0x00000000

Read/write data into R3.

READ10

0x10

RO

32

0xFFFFFFFF

Not R0.

READ14

0x14

RO

32

0x00000000

R0 and R1.

READ18

0x18

RO

32

0x00000000

R1 or R2.

READ1C

0x1C

RO

32

0x00000000

R2 xor R3.

READ20

0x20

RO

32

0x00000000

R0 and R1 and R2 and R3.

READ24

0x24

RO

32

0x00000000

R0 or R1 or R2 or R3.

READ28

0x28

RO

32

0x00000000

R0 xor R1 xor R2 xor R3.

Reserved

0x2C-0xFDC

R/W

32

0x00000000

Read as zero. Write has no effect.

PERIPHERALID0

0xFE0

RO

8

0x06

Peripheral ID register 0.

PERIPHERALID1

0xFE4

RO

8

0x18

Peripheral ID register 1.

PERIPHERALID2

0xFE8

RO

8

0x04

Peripheral ID register 2.

PERIPHERALID3

0xFEC

RO

8

0x00

Peripheral ID register 3.

PRIMECELLID0

0xFF0

RO

8

0x0D

PrimeCell ID register 0.

PRIMECELLID1

0xFF4

RO

8

0xF0

PrimeCell ID register 1.

PRIMECELLID2

0xFF8

RO

8

0x05

PrimeCell ID register 2.

PRIMECELLID3

Base + 0xFFC

RO

8

0xB1

PrimeCell ID register 3.

The functionality in Table 4.11 is the same as the retry slave described in Example retry slave, except there is no requirement to generate wait states and responses, and all data is a fixed size (32-bit).

Note

Address locations 0x2C-0xFDC read as zero and perform no operation when written to.

The peripheral ID information is arranged as four 8-bit registers that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a 32-bit read-only register. Table 4.12 lists the format of this information and the values for the peripheral.

Table 4.12. Peripheral ID format

Register field

Description

Part number [11:0]

This identifies the peripheral. The three digit product code 0x806 is used.

Designer ID [19:12]

This is the identification of the designer. ARM Limited is 0x41, ASCII A.

Revision [23:20]

This is the revision number of the peripheral. The revision number starts from 0.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

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