AMBA Design Kit Technical Reference Manual 4.4.1. Programmer’s model

4.4.1. Programmer’s model

Table 4.13 lists the watchdog registers.

Table 4.13. Watchdog unit register summary

Name	Base offset	Type	Width	Reset value	Description
WDOGLOAD	`0x00`	R/W	32	`0xFFFFFFFF`	See Watchdog Load Register
WDOGVALUE	`0x04`	RO	32	`0xFFFFFFFF`	See Watchdog Value Register
WDOGCONTROL	`0x08`	R/W	2	`0x0`	See Watchdog Control Register
WDOGINTCLR	`0x0C`	WO	-	-	See Watchdog Clear Interrupt Register
WDOGRIS	`0x10`	RO	1	`0x0`	See Watchdog Raw Interrupt Status Register
WDOGMIS	`0x14`	RO	1	`0x0`	See Watchdog Interrupt Status Register
WDOGLOCK	`0xC00`	R/W	32	`0x0`	See Watchdog Lock Register
WDOGITCR	`0xF00`	R/W	1	`0x0`	See Watchdog Integration Test Control Register
WDOGITOP	`0xF04`	WO	2	`0x0`	See Watchdog Integration Test Output Set Register
WDOGPERIPHID0	`0xFE0`	RO	8	`0x05`	See Peripheral Identification Register 0
WDOGPERIPHID1	`0xFE4`	RO	8	`0x18`	See Peripheral Identification Register 1
WDOGPERIPHID2	`0xFE8`	RO	8	`0x04`	See Peripheral Identification Register 2
WDOGPERIPHID3	`0xFEC`	RO	8	`0x00`	See Peripheral Identification Register 3
WDOGPCELLID0	`0xFF0`	RO	8	`0x0D`	See PrimeCell Identification Register 0
WDOGPCELLID1	`0xFF4`	RO	8	`0xF0`	See PrimeCell Identification Register 1
WDOGPCELLID2	`0xFF8`	RO	8	`0x05`	See PrimeCell Identification Register 2
WDOGPCELLID3	`0xFFC`	RO	8	`0xB1`	See PrimeCell Identification Register 3

The following registers are described in this section:

Watchdog Load Register

The WDOGLOAD Register is a 32-bit register containing the value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. The minimum valid value for WDOGLOAD is 1.

Watchdog Value Register

The WDOGVALUE Register gives the current value of the decrementing counter.

Watchdog Control Register

The WDOGCONTROL Register is a read/write register that enables the software to control the watchdog unit. Figure 4.7 shows the register bit assignments.

Figure 4.7. WDOGCONTROL Register bit assignments

Table 4.14 lists the register bit assignments.

Table 4.14. WDOGCONTROL Register bit assignments

Bits	Name	Function
[31:2]	-	Reserved, read undefined, must read as zeros.
[1]	RESEN	Enable Watchdog reset output, WDOGRES. Acts as a mask for the reset output. Set HIGH to enable the reset, and LOW to disable the reset.
[0]	INTEN	Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and the interrupt, and set LOW to disable the counter and interrupt. Reloads the counter from the value in WDOGLOAD when the interrupt is enabled, and was previously disabled.

Watchdog Clear Interrupt Register

A write of any value to the WDOGINTCLR Register clears the watchdog interrupt, and reloads the counter from the value in WDOGLOAD.

Watchdog Raw Interrupt Status Register

The WDOGRIS Register is read-only. It indicates the raw interrupt status from the counter. This value is ANDed with the interrupt enable bit from the control register to create the masked interrupt, that is passed to the interrupt output pin. Figure 4.8 shows the register bit assignments.

Figure 4.8. WDOGRIS Register bit assignments

Table 4.15 lists the register bit assignments.

Table 4.15. WDOGRIS Register bit assignments

Bits	Name	Function
[31:1]	-	Reserved, read undefined, must read as zeros
[0]	Raw Watchdog Interrupt	Raw interrupt status from the counter

Watchdog Interrupt Status Register

The WDOGMIS Register is read-only. It indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the INTEN bit from the control register, and is the same value that is passed to the interrupt output pin. Figure 4.9 shows the register bit assignments.

Figure 4.9. WDOGMIS Register bit assignments

Table 4.16 lists the register bit assignments.

Table 4.16. WDOGMIS Register bit assignments

Bits	Name	Function
[31:1]	-	Reserved, read undefined, must read as zeros
[0]	Watchdog Interrupt	Enabled interrupt status from the counter

Watchdog Lock Register

The WDOGLOCK Register is write-only. Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write accesses. A read from this register returns only the bottom bit:

0 indicates that write access is enabled, not locked
1 indicates that write access is disabled, locked.

Figure 4.10 shows the register bit assignments.

Figure 4.10. WDOGLOCK Register bit assignments

Table 4.17 lists the bit assignments for the WDOGLOCK register.

Table 4.17. WDOGLOCK Register bit assignments

Bits	Name	Function
[31:1]	Enable register writes	Enable write access to all other registers by writing `0x1ACCE551`. Disable write access by writing any other value.
[0]	Register write enable status	0 = write access to all other registers is enabled, default 1 = write access to all other registers is disabled

Bits

Name

Function

[31:1]

Enable register writes

Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value.

[0]

0 = write access to all other registers is enabled, default

1 = write access to all other registers is disabled

Watchdog Integration Test Control Register

The WDOGITCR Register is read/write. It is a single-bit register that enables integration test mode. When in this mode, the masked interrupt output, WDOGINT, and reset output, WDOGRES, are directly controlled by the test output set register.

Figure 4.11 shows the register bit assignments.

Figure 4.11. WDOGITCR Register bit assignments

Table 4.18 lists the register bit assignments.

Table 4.18. WDOGITCR Register bit assignments

Bits	Name	Function
[31:1]	-	Reserved, read undefined, must read as zeros
[0]	Integration Test Mode Enable	When set HIGH, places the Watchdog into integration test mode

Watchdog Integration Test Output Set Register

The WDOGITOP Register is write-only. When in integration test mode, the enabled interrupt output and reset output are driven directly from the values in this register. Figure 4.12 shows the register bit assignments.

Figure 4.12. WDOGITOP Register bit assignments

Table 4.19 lists the register bit assignments.

Table 4.19. WDOGITOP Register bit assignments

Bits	Name	Function
[31:2]	-	Reserved, read undefined, must read as zeros
[1]	Integration Test WDOGINT value	Value output on WDOGINT when in Integration Test Mode
[0]	Integration Test WDOGRES value	Value output on WDOGRES when in Integration Test Mode

Peripheral Identification Registers

The WDOGPERIPHID0-3 registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options for the peripheral:

Part number [11:0]: This identifies the peripheral. The three digit product code 0x805 is used for the watchdog unit.
Designer [19:12]: This is the identification of the designer. ARM Limited is 0x41, ASCII A.
Revision number [23:20]: This is the revision number of the peripheral. The revision number starts from 0.
Configuration [31:24]: This is the configuration option of the peripheral. The configuration value is 0.

Figure 4.13 shows the register bit assignments.

Figure 4.13. WDOGPERIPHID0-3 Register bit assignments

Note

When you design a system memory map you must remember that the register has a 4KB-memory footprint. All memory accesses to the peripheral identification registers must be 32-bit, using the LDR and STR instructions.

The four 8-bit peripheral identification registers are described in the following subsections:

Peripheral Identification Register 0

The WDOGPERIPHID0 Register is hard-coded and the fields within the register determine the reset value. Table 4.20 lists the register bit assignments.

Table 4.20. WDOGPERIPHID0 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:0]	PartNumber0	These bits read back as `0x05`

Peripheral Identification Register 1

The WDOGPERIPHID1 Register is hard-coded and the fields within the register determine the reset value. Table 4.21 lists the register bit assignments.

Table 4.21. WDOGPERIPHID1 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:4]	Designer0	These bits read back as `0x1`
[3:0]	PartNumber1	These bits read back as `0x08`

Peripheral Identification Register 2

The WDOGPERIPHID2 Register is hard-coded and the fields within the register determine the reset value. Table 4.22 lists the register bit assignments.

Table 4.22. WDOGPERIPHID2 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:4]	Revision	These bits read back as `0x0`
[3:0]	Designer1	These bits read back as `0x4`

Peripheral Identification Register 3

The WDOGPERIPHID3 Register is hard-coded and the fields within the register determine the reset value. Table 4.23 lists the register bit assignments.

Table 4.23. WDOGPERIPHID3 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:0]	Configuration	These bits read back as `0x00`

PrimeCell Identification Registers

The WDOGPCELLID0-3 Registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The WDOGPCELLID Register is set to 0xB105F00D. Figure 4.14 shows the register bit assignments.

Figure 4.14. WDOGPCELLID0-3 Register bit assignments

The four, 8-bit PrimeCell identification registers are described in the following subsections:

PrimeCell Identification Register 0

The WDOGPCELLID0 Register is hard-coded and the fields within the register determine the reset value. Table 4.24 lists the register bit assignments.

Table 4.24. WDOGPCELLID0 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:0]	WdogPCellID0	These bits read back as `0x0D`

PrimeCell Identification Register 1

The WDOGPCELLID1 Register is hard-coded and the fields within the register determine the reset value. Table 4.25 lists the register bit assignments.

Table 4.25. WDOGPCELLID1 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:0]	WdogPCellID1	These bits read back as `0xF0`

PrimeCell Identification Register 2

The WDOGPCELLID2 Register is hard-coded and the fields within the register determine the reset value. Table 4.26 lists the register bit assignments.

Table 4.26. WDOGPCELLID2 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:0]	WdogPCellID2	These bits read back as `0x05`

PrimeCell Identification Register 3

The WDOGPCELLID3 register is hard-coded and the fields within the register determine the reset value. Table 4.27 lists the register bit assignments.

Table 4.27. WDOGPCELLID3 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined, must read as zeros
[7:0]	WdogPCellID3	These bits read back as `0xB1`

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