4.5.2. Operation

Each timer has an identical set of registers as shown in Table 4.29. The operation of each timer is identical. The timer is loaded by writing to the load register and, if enabled, counts down to zero. When a counter is already running, writing to the load register causes the counter to immediately restart at the new value. Writing to the background load value has no effect on the current count. The counter continues to decrement to zero, and then recommences from the new load value, if in periodic mode, and one shot mode is not selected.

When zero is reached, an interrupt is generated. The interrupt can be cleared by writing to the clear register. If One Shot Mode is selected, the counter halts on reaching zero until the you deselect One Shot Mode, or write a new Load value. Otherwise, after reaching a zero count, if the timer is operating in free-running mode it continues to decrement from its maximum value. If periodic timer mode is selected, the timer reloads the count value from the Load Register and continues to decrement. In this mode the counter effectively generates a periodic interrupt. The mode is selected by a bit in the Timer Control Register. See Table 4.30. At any point, the current counter value can be read from the Current Value Register. The counter is enabled by a bit in the Control Register. At reset, the counter is disabled, the interrupt is cleared, and the load register is set to zero. The mode and prescale values are set to free-running, and clock divide of 1 respectively. Figure 4.16 shows a block diagram of the free-running timer module.

Figure 4.16. Free-running timer block

The timer clock enable is generated by a prescale unit. The enable is then used by the counter to create a clock with a timing of one of the following:

Figure 4.17 shows how the timer clock frequency is selected in the prescale unit. This enables you to clock the timer at different frequencies.

Figure 4.17. Prescale clock enable generation

Note

This selection is in addition to any similar facility already provided as part of any clock generation logic external to the Timers.

Interrupt generation

An interrupt is generated when the full 32-bit counter reaches zero, and is only cleared when the TimerXClear location is written to. A register holds the value until the interrupt is cleared. The most significant carry bit of the counter detects the counter reaching zero.

You can mask interrupts by writing 0 to the Interrupt Enable bit in the Control register. Both the raw interrupt status, prior to masking, and the final interrupt status, after masking, can be read from status registers.

The interrupts from the individual counters, after masking, are logically ORed into a combined interrupt, TIMINTC, provides an additional output from the Timer peripheral.

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