4.5.3. Clocking

The timers have two clock inputs, PCLK and TIMCLK. PCLK is the main APB system clock, and is used by the register interface. TIMCLK is the input to the prescale units and the decrementing counters. A pulse on TIMCLK must be qualified by the appropriate TIMCLKENx being HIGH.

The design of the timers assumes that PCLK and TIMCLK are synchronous. To enable the counter to operate from a lower effective frequency than that at which PCLK is running, you can do either of the following:

This provision of two clock inputs enables the counters to continue to run while the APB system is in a sleep state whereby PCLK is disabled. The changeover periods when PCLK is disabled and enabled must be handled by external system control logic, to ensure that the PCLK and TIMCLK inputs are fed with synchronous signals when any register access is to occur.

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