4.5.4. Programmer’s model

Table 4.29 lists the timer registers.

Table 4.29. Timer register summary

Name

Base

offset

Type

Width

Reset

value

Description

TIMER1LOAD

0x00

R/W

32

0x00000000

See Load Register

TIMER1VALUE

0x04

RO

32

0xFFFFFFFF

See Current Value Register

TIMER1CONTROL

0x08

R/W

8

0x20

See Timer Control Register

TIMER1INTCLR

0x0C

WO

-

-

See Interrupt Clear Register

TIMER1RIS

0x10

RO

1

0x0

See Raw Interrupt Status Register

TIMER1MIS

0x14

RO

1

0x0

See Interrupt Status Register

TIMER1BGLOAD

0x18

R/W

32

0x00000000

See Background Load Register

TIMER2LOAD

0x20

R/W

32

0x00000000

See Load Register

TIMER2VALUE

0x24

RO

32

0xFFFFFFFF

See Current Value Register

TIMER2CONTROL

0x28

R/W

8

0x20

See Timer Control Register

TIMER2INTCLR

0x2C

WO

-

-

See Interrupt Clear Register

TIMER2RIS

0x30

RO

1

0x0

See Raw Interrupt Status Register

TIMER2MIS

0x34

RO

1

0x0

See Interrupt Status Register

TIMER2BGLOAD

0x38

R/W

32

0x00000000

See Background Load Register

TIMERITCR

0xF00

R/W

1

0x0

See Integration Test Control Register

TIMERITOP

0xF04

WO

2

0x0

See Integration Test Output Set Register

TIMERPERIPHID0

0xFE0

RO

8

0x04

See Peripheral Identification Register 0

TIMERPERIPHID1

0xFE4

RO

8

0x18

See Peripheral Identification Register 1

TIMERPERIPHID2

0xFE8

RO

8

0x04

See Peripheral Identification Register 2

TIMERPERIPHID3

0xFEC

RO

8

0x00

See Peripheral Identification Register 3

TIMERPCELLID0

0xFF0

RO

8

0x0D

See PrimeCell Identification Register 0

TIMERPCELLID1

0xFF4

RO

8

0xF0

See PrimeCell Identification Register 1

TIMERPCELLID2

0xFF8

RO

8

0x05

See PrimeCell Identification Register 2

TIMERPCELLID3

0xFFC

RO

8

0xB1

See PrimeCell Identification Register 3

Load Register

The TIMERXLOAD Register is a 32-bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero.

When this register is written to directly, the current count is immediately reset to the new value at the next rising edge of TIMCLK that is enabled by TIMCLKEN.

The value in this register is also overwritten if the TIMERXBGLOAD Register is written to, but the current count is not immediately affected.

If values are written to both the TIMERXLOAD and TIMERXBGLOAD Registers before an enabled rising edge on TIMCLK, the following occurs:

  1. On the next enabled TIMCLK edge, the value written to the TIMERXLOAD value replaces the current count value.

  2. Then, each time the counter reaches zero, the current count value is reset to the value written to TIMERXBGLOAD.

Reading from the TIMERXLOAD Register at any time after the two writes have occurred retrieves the value written to TIMERXBGLOAD. That is, the value read from TIMERXLOAD is always the value that takes effect for Periodic mode after the next time the counter reaches zero.

Current Value Register

The TIMERXVALUE Register gives the current value of the decrementing counter.

Timer Control Register

The TIMERXCONTROL Register is a read/write register. Figure 4.18 shows the register bit assignments.

Figure 4.18. TIMERXCONTROL Register bit assignments

Table 4.30 lists the register bit assignments.

Table 4.30. TIMERXCONTROL Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must read as zeros

[7]

Timer Enable

Enable bit:

0 = Timer disabled, default

1 = Timer enabled.

[6]

Timer Mode

Mode bit:

0 = Timer is in free-running mode, default

1 = Timer is in periodic mode.

[5]

Interrupt Enable

Interrupt Enable bit:

0 = Timer Interrupt disabled

1 = Timer Interrupt enabled, default.

[4]

RESERVED

Reserved bit, do not modify, and ignore on read

[3:2]

TimerPre

Prescale bits:

00 = 0 stages of prescale, clock is divided by 1, default

01 = 4 stages of prescale, clock is divided by 16

10 = 8 stages of prescale, clock is divided by 256

11 = Undefined, do not use.

[1]

Timer Size

Selects 16/32 bit counter operation:

0 = 16-bit counter, default

1 = 32-bit counter.

[0]

One Shot Count

Selects one-shot or wrapping counter mode:

0 = wrapping mode, default

1 = one-shot mode.

Interrupt Clear Register

Any write to the TIMERXINTCLR Register clears the interrupt output from the counter.

Raw Interrupt Status Register

This register is read-only. It indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt, that is passed to the interrupt output pin. Figure 4.19 shows the register bit assignments.

Figure 4.19. TIMERXRIS Register bit assignments

Table 4.31 lists the register bit assignments.

Table 4.31. TIMERXRIS Register bit assignments

Bits

Name

Function

[31:1]

-

Reserved, read undefined, must read as zeros

[0]

Raw Timer Interrupt

Raw interrupt status from the counter

Interrupt Status Register

The TIMERXMIS Register is read-only. It indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the timer interrupt enable bit from the Timer Control Register, and is the same value that is passed to the interrupt output pin. Figure 4.20 shows the register bit assignments.

Figure 4.20. TIMERXMIS Register bit assignments

Table 4.32 lists the register bit assignments.

Table 4.32. TIMERXMIS Register bit assignments

Bits

Name

Function

[31:1]

-

Reserved, read undefined, must read as zeros

[0]

Timer Interrupt

Enabled interrupt status from the counter

Background Load Register

The TIMERXBGLOAC Register is 32-bits and contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero.

This register provides an alternative method of accessing the TIMERXLOAD Register. The difference is that writes to TIMERXBGLOAD do not cause the counter to immediately restart from the new value.

Reading from this register returns the same value returned from TIMERXLOAD. See Load Register for more details.

Integration Test Control Register

The TIMERITCR Register is read/write. It is a single-bit register that enables integration test mode. When in this mode, the masked interrupt outputs are directly controlled by the Integration Test Output Set Register. The combined interrupt output TIMINTC then becomes the logical OR of the bits set in the Integration Test Output Set Register. Figure 4.21 shows the register bit assignments.

Figure 4.21. TIMERITCR Register bit assignments

Table 4.33 lists the register bit assignments.

Table 4.33. TIMERITCR Register bit assignments

Bits

Name

Function

[31:1]

-

Reserved, read undefined, must read as zeros

[0]

Integration Test Mode Enable

When set HIGH, places the Timers into integration test mode

Integration Test Output Set Register

When in integration test mode, the enabled interrupt outputs are driven directly from the values in this write-only register, TIMERITOP. Figure 4.22 shows the register bit assignments.

Figure 4.22. TIMERITOP Register bit assignments

Table 4.34 lists the register bit assignments.

Table 4.34. TIMERITOP Register bit assignments

Bits

Name

Function

[31:2]

-

Reserved, read undefined, must read as zeros

[1]

Integration Test TIMINT2 value

Value output on TIMINT2 when in Integration Test Mode

[0]

Integration Test TIMINT1 value

Value output on TIMINT1 when in Integration Test Mode

Peripheral Identification Registers

The TIMERPERIPHID0-3 Registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options of the peripheral:

Part number [11:0]

This identifies the peripheral. The three digit product code 0x804 is used for the timer.

Designer [19:12]

This is the identification of the designer. ARM Limited is 0x41, ASCII A.

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 4.23 shows the register bit assignments.

Figure 4.23. Peripheral identification register bit assignments

Note

When you design a system memory map, you must remember that the register has a 4KB-memory footprint.

The 4-bit revision number is implemented by instantiating a component called RevisionAnd four times with its inputs tied off as appropriate, and the output sent to the read multiplexor.

All memory accesses to the peripheral identification registers must be 32-bit, using the LDR and STR instructions.

The four, 8-bit peripheral identification registers are described in the following subsections:

Peripheral Identification Register 0

The TIMERPERIPHID0 Register is hard-coded and the fields within the register determine the reset value. Table 4.35 lists the register bit assignments.

Table 4.35. TIMERPERIPHID0 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

Partnumber0

These bits read back as 0x04

Peripheral Identification Register 1

The TIMERPERIPHID1 Register is hard-coded and the fields within the register determine the reset value. Table 4.36 lists the register bit assignments.

Table 4.36. TIMERPERIPHID1 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must read as zeros

[7:4]

Designer0

These bits read back as 0x1

[3:0]

Partnumber1

These bits read back as 0x08

Peripheral Identification Register 2

The TIMERPERIPHID2 Register is hard-coded and the fields within the register determine the reset value. Table 4.37 lists the register bit assignments.

Table 4.37. TIMERPERIPHID2 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must read as zeros

[7:4]

Revision

These bits read back as 0x0

[3:0]

Designer1

These bits read back as 0x4

Peripheral Identification Register 3

The TIMERPERIPHID3 Register is hard-coded and the fields within the register determine the reset value. Table 4.38 lists the register bit assignments.

Table 4.38. TIMERPERIPHID3 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

Configuration

These bits read back as 0x0

PrimeCell Identification Registers

The TIMERPCELLID0-3 Registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. The read-only registers can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system. Figure 4.24 shows the register bit assignments.

Figure 4.24. PrimeCell identification register bit assignments

The four, 8-bit registers are described in the following subsections:

PrimeCell Identification Register 0

The TIMERPCELLID0 Register is hard-coded and the fields within the register determine the reset value. Table 4.39 lists the register bit assignments.

Table 4.39. TIMERPCELLID0 Register bit assignments

Bits

Name

Function

[31:8]

-

Reserved, read undefined, must read as zeros

[7:0]

TimerPCellID0

These bits read back as 0x0D

PrimeCell Identification Register 1

The TIMERPCELLID1 Register is hard-coded and the fields within the register determine the reset value. Table 4.40 lists the register bit assignments.

Table 4.40. TIMERPCELLID1 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read undefined, must read as zeros

[7:0]

TimerPCellID1

Read

These bits read back as 0xF0

PrimeCell Identification Register 2

The TIMERPCELLID2 Register is hard-coded and the fields within the register determine the reset value. Table 4.41 lists the register bit assignments.

Table 4.41. TIMERPCELLID2 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read undefined, must read as zeros

[7:0]

TimerPCellID2

Read

These bits read back as 0x05

PrimeCell Identification Register 3

The TIMERPCELLID3 Register is hard-coded and the fields within the register determine the reset value. Table 4.42 lists the register bit assignments.

Table 4.42. TIMERPCELLID3 Register bit assignments

Bits

Name

Type

Function

[31:8]

-

-

Reserved, read undefined, must read as zeros

[7:0]

TimerPCellID3

Read

These bits read back as 0xB1

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