4.5.5. Signal descriptions

Table 4.43 lists the non-AMBA signals used by the timer.

Table 4.43. Timer signals

Signal

Type

Direction

Description

TIMCLK

Timer clock

Input

The timer clock input. This must be synchronous to PCLK for normal operation.

TIMCLKEN1

Timer 1 clock enable

Input

The enable for the timer1 clock input. The counter will only decrement on a rising edge of TIMCLK when TIMCLKEN1 is HIGH.

TIMCLKEN2

Timer 2 clock enable

Input

The enable for the timer clock input. The counter will only decrement on a rising edge of TIMCLK when TIMCLKEN2 is HIGH.

TIMINT1

Counter 1 interrupt

Output

Active HIGH interrupt signal to the interrupt controller module. This signal indicates an interrupt has been generated by counter 1 having being decremented to zero.

TIMINT2

Counter 2 interrupt

Output

Active HIGH interrupt signal to the interrupt controller module. This signal indicates an interrupt has been generated by counter 2 having being decremented to zero.

TIMINTC

Combined Counter Interrupt

Output

Active HIGH interrupt signal to the interrupt controller module. This signal indicates an interrupt has been generated by either counter having being decremented to zero, and is the logical OR of TIMINT1 and TIMINT2.

Note

For a description of the AMBA signals used by the timer, see AMBA signals.

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