5.5.1. Programmer’s model

The FileRdMaster uses the following Verilog parameters:

InputFileName

This is the name of the stimulus data file to be read. If the file is not found, simulation is aborted. The default file name is filestim.m2d.

MessageTag

A string that is prepended to all stimulation messages from this FileRdMaster. This tag can be used to differentiate between messages from multiple file reader masters in a system. The default message tag is FileReader:.

StimArraySize

The size, in words, of the internal array used to store the stimulus data. This value has a direct effect on the simulation startup time and memory requirement. This value must be large enough to store the whole data file. If the data file is larger than the array, simulation is aborted. The default value is 5000.

The following AHB-Lite FRM functions are described in this section:

Write command

The write command W starts a write burst and can be followed by one or more S vectors. For bursts of fixed length, the Burst field determines the number of S vectors. For bursts of undefined length, there can be any number of S vectors as long as they do not cause the address to cross a 1K boundary.

Figure 5.6 shows the write command timing diagram.

Figure 5.6. Write command timing

The write command operates as follows:

Cycle 1

The file reader sets up the control signals from the command and asserts HWRITE. HTRANS is NONSEQ to indicate the first transfer of the burst. The Data field is stored and ready to be driven during the data phase.

If HREADY is asserted, the file reader proceeds to the second control phase.

Cycle 2

This is the first data phase in which the data is driven for the previous cycle. Unless the Burst field specifies a single transfer, the file reader calculates the next address based on the Size and Burst values.

Read command

The read command R starts a read burst and can be followed by one or more S vectors. For bursts of fixed length, the Burst field determines the number of S vectors. For bursts of undefined length, there can be any number of S vectors as long as they do not cause the address to cross a 1K boundary.

Figure 5.7 shows the read command timing diagram.

Figure 5.7. Read command timing

The read command operates as follows:

Cycle 1

The file reader sets up the control signals from the command and deasserts HWRITE. HTRANS is NONSEQ to indicate the first transfer of a burst.

If HREADY is asserted, the file reader proceeds to the second control phase.

Cycle 2

The data read for the previous cycle is compared with the Data field after applying the mask and byte lane strobes. Any differences are reported to the simulation environment. Unless the Burst field indicates a single transfer, the file reader calculates the next address based on the Size and Burst values.

Sequential command

The sequential command S is a vector that provides data for a single beat within the burst. The file reader calculates the required address. A sequential command is valid when a burst transfer is started by a read or write command.

Figure 5.8 shows the sequential command timing diagram.

Figure 5.8. Sequential command timing

A sequential command is valid when a burst transfer has been started by a Read or Write command:

Cycle n

The file reader drives the calculated address, and HTRANS is SEQ to indicate the remaining transfers of the burst.

If HREADY is asserted, the file reader proceeds to the second control phase.

Cycle n + 1

In a write burst, the file reader drives the Data field data and ignores the Mask field.

In a read burst, the file reader applies the Mask and Bstrb fields to the input data and then compares the Data field with the input data. The file reader reports differences between the expected data and the read data to the simulation environment.

Busy command

The busy command B inserts either a BUSY transfer or a BUSY cycle, depending on the Wait field. A busy command is valid when a burst transfer is started by a read or write command.

During a burst with the Wait field not specified, the busy command inserts a single HCLK BUSY transfer on the AHB. An INCR burst can have a busy command after its last transfer while the master determines whether it has another transfer to complete.

Figure 5.9 shows the busy command timing diagram.

Figure 5.9. Busy transfer timing

Cycle n

The file reader drives the calculated address and HTRANS is BUSY.

Cycle n + 1

The file reader proceeds to the next control phase. Data is ignored.

During a burst with the Wait field specified, the busy command inserts a complete AHB transfer as Figure 5.10 shows.

Figure 5.10. Busy cycle timing

The address phase is extended by wait states because of the data phase of a previous transfer, if present.

Idle command

The idle command I performs either an IDLE transfer or an IDLE cycle, depending on the Wait field. The options enable you to set up the control information during the IDLE transfer, and to specify if the transfer is locked or unlocked.

If the Wait field is not specified, the idle command inserts a single HCLK cycle IDLE transfer on the AHB, as Figure 5.11 shows.

Figure 5.11. Idle transfer timing

Cycle 1

HTRANS is IDLE and the control signals take the default values, except for those specified in the command.

Cycle 2

The file reader proceeds to the next control phase. Data is ignored.

If the Wait field is specified, the idle command inserts a complete AHB transfer as Figure 5.12 shows. The address phase is extended by wait states due to the data phase of a previous transfer, if present.

Figure 5.12. Idle cycle timing

Cycle 1

HTRANS is set to IDLE and the control signals are set to the default values, except for those specified in the command.

Cycle 2

If the Wait field is not specified, or the Wait field is specified and HREADY is asserted, then the file reader proceeds to the next control phase. Data is ignored.

Poll command

The poll command P continually reads the input data until it matches the value in the Data field or until the number of reads equals the number in the Timeout field. If the input data does not match after the Timeout number, the file reader reports an error. Not specifying a TimeOut value or specifying a Timeout value of 0 causes the poll command to read continually until the data matches the required value. The poll command is only for INCR or SINGLE burst types and for aligned addresses.

Figure 5.13 shows the poll command.

Figure 5.13. Poll command timing

The poll command operates as follows:

Cycle 1

The file reader sets up a read of the single address in the Address field.

If HREADY is asserted, the file reader proceeds to the second control phase.

Cycle 2

The file reader issues an IDLE transfer, reads the data for the previous address value.

Loop command

The loop command L repeats the last command a number of times. When the burst type is INCR or SINGLE, a loop command must follow only a write or read. Because the file reader has a 32-bit counter, the maximum number of loops is 232 -1.

Note

Commands that do not directly represent bus transactions, for example, the simulation comment command C, are not looped. Consecutive loops are cumulative and not multiplicative. For example:

I 0x4000
C Commencing IDLES
L 1000
L 1000

This sequence performs an IDLE to address 0x4000, generates the comment, and then performs 2000 further IDLE access to address 0x4000.

Comment command

The comment command C sends a message to the simulation window.

Quit command

The quit command Q causes the simulation to terminate immediately. Additionally, the quit command gives a summary of the number of commands and errors.

Resp field

The Resp field tests for the expected response. The Resp field must be present on a command that is expected to receive an Error response from a slave.

If the Resp field is set to Errorcont or Errorcanc and an ERROR response is received, no warning is given. If the Resp field is set to Errorcont or Errorcanc and an ERROR response is not received, a simulation warning is generated.

If an error occurs during a burst transfer and the Resp field is set to Errorcont, the burst continues.

If an error occurs during a burst transfer and the Resp field is set to Errorcanc, the burst is cancelled. No attempt is made to retransmit the erroneous transfer. The stimulus file does not have to contain the remaining transfers in the burst. An IDLE transfer is always inserted during the ultimate cycle of the error response if the burst is to be cancelled.

Clock and reset

The file reader is synchronous with the AHB bus clock signal HCLK and is reset by the AHB reset signal HRESETn.

Error reporting at runtime

An error can occur in the following circumstances:

  • a read transfer where the expected data does not match the actual data

  • a transfer that receives an AHB ERROR response and the Error field is not set

  • a transfer where the Error field is set and the transfer does not receive an AHB ERROR response

  • a Poll command where the expected data is not received within the timeout number of attempts

  • the stimulus file is longer than the array size allocated.

When an error is reported, the line number of the corresponding command on the input file is reported to the simulation window.

End of stimulus

A summary of the number of commands and errors is given when any of the following is reached:

  • a quit command

  • end of input file

  • end of the internal command array.

Simulation is terminated when a Q command is encountered.

If the end of the stimulus is reached, all AHB signals are set to zero. This implies IDLE read transfers to address 0x00.

If the end of the internal command array is reached and the end of the stimulus file has not been reached, a warning is given, and all AHB signals are set to zero. This implies IDLE read transfers to address 0x00.

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