5.6.1. Signal descriptions

Table 5.18 lists the non-AMBA signals used by the Ticbox module.

Table 5.18. Ticbox module signals

Signal

Type

Direction

Description

nRESET

External reset

Input

Active LOW external reset input. Used to control the operation of the Ticbox module.

TESTACK

Test acknowledge

Input

Indicates that the test bus has been granted and also that a test access has been completed.

TESTBUS[31:0]

Test data bus

Input/output

32-bit bidirectional test port.

TESTCLK

Test mode clock

Input

This is the system clock HCLK in test mode. All the test interface transactions are timed using this signal.

TESTREQA

Test request A

Output

Indicates test vector mode. Refer to the test interface chapter in the AMBA Specification for further information about the test protocol. It is driven early in the LOW phase of TESTCLK and held to the falling edge of TESTCLK.

TESTREQB

Test request B

Output

Indicates test vector mode. See the test interface chapter of the AMBA Specification for further information about the test protocol. It is driven early in the LOW phase of TESTCLK and held to the falling edge of TESTCLK.

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