AMBA Design Kit Technical Reference Manual

Revision: r3p0

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on the product
Feedback on this book
1. Introduction
1.1. About the ADK
1.2. AMBA signals
1.2.1. AMBA AHB signals
1.2.2. AMBA APB signals
1.3. Product revisions
2. Functional Overview
2.1. About the ADK toolkit
2.2. ADK components
2.2.1. AHB components
2.2.2. APB components
2.2.3. Behavioral models
2.3. Example systems
2.3.1. FRM-based AMBA system, EASY_FRBM
2.3.2. ARM7TDMI-based example AMBA system, EASY_ARM7
2.3.3. ARM922T-based example AMBA system, EASY_ML
2.3.4. Address map
3. AHB Components
3.1. Reset controller
3.1.1. Signal descriptions
3.2. Arbiter
3.2.1. Operation
3.2.2. Signal descriptions
3.3. Default slave
3.3.1. Signal descriptions
3.4. Master-to-slave multiplexor
3.4.1. Signal descriptions
3.5. Slave-to-master multiplexor
3.5.1. Signal descriptions
3.6. Example retry slave
3.6.1. Signal descriptions
3.7. Example static memory interface
3.7.1. SMI programmer’s model
3.7.2. Test interface controller
3.7.3. TIC programmer’s model
3.7.4. Signal descriptions
3.8. Bus matrix
3.8.1. Key features
3.8.2. Bus Matrix configurability
3.8.3. Relationship between the AMBA Designer and Bus Matrix
3.8.4. BusMatrix module
3.8.5. Operation
3.8.6. Programmer's model
3.8.7. Block functionality
3.8.8. Arbitration and locked transfers
3.8.9. Address map
3.8.10. Signal descriptions
3.9. System decoder
3.9.1. Programmer's model
3.9.2. Signal descriptions
3.10. APB bridge
3.10.1. Ahb2Apb bridge
3.10.2. AhbToAPB bridge
3.11. Example bus master
3.11.1. Programmer's model
3.11.2. Signal descriptions
3.12. Synchronous AHB to AHB bridge
3.12.1. Bridge designations
3.12.2. Typical applications
3.12.3. Programmer's model
3.12.4. Optional additional blocks
3.12.5. Signal descriptions
3.13. Asynchronous AHB-AHB bridge
3.13.1. Programmer's model
3.13.2. Signal descriptions
3.14. AHB-Lite to AHB wrapper
3.14.1. Programmer's model
3.15. Interrupt controller
3.15.1. Programmer’s model
3.15.2. Signal descriptions
3.16. 64-bit to 32-bit downsizer
3.16.1. Programmer's model
3.16.2. Signal descriptions
3.17. 64-bit to 32-bit funnel
3.17.1. Programmer's model
3.17.2. Signal descriptions
4. APB Components
4.1. Remap and pause controller
4.1.1. Programmer’s model
4.1.2. Signal descriptions
4.2. Example APB slave
4.2.1. Programmer’s model
4.2.2. Signal descriptions
4.3. Peripheral to bridge multiplexor
4.3.1. Signal descriptions
4.4. Watchdog unit
4.4.1. Programmer’s model
4.4.2. Signal descriptions
4.5. Dual input timer
4.5.1. Functional description
4.5.2. Operation
4.5.3. Clocking
4.5.4. Programmer’s model
4.5.5. Signal descriptions
5. Behavioral Models
5.1. External RAM,
5.1.1. Programmer’s model
5.1.2. Signal descriptions
5.2. Internal memory
5.2.1. Programmer’s model
5.2.2. Signal descriptions
5.3. External ROM
5.3.1. Programmer’s model
5.3.2. Signal descriptions
5.4. Tube
5.4.1. Signal descriptions
5.5. AHB file reader master
5.5.1. Programmer’s model
5.5.2. Command syntax
5.5.3. File preprocessing
5.6. Test interface driver
5.6.1. Signal descriptions
5.6.2. User-defined settings
6. PrimeCell GPIO
6.1. Operation
6.2. Integration within ADK
A. AHB-Lite Overview
A.1. About AHB-Lite
A.1.1. Specification
A.1.2. Compatibility
A.2. AHB-Lite master
A.2.1. AHB-Lite advantages
A.2.2. AHB-Lite conversion to full AHB
A.3. AHB-Lite slaves

List of Figures

1. Key to timing diagram conventions
2.1. EASY_FRBM example AMBA system
2.2. EASY_ARM7 example AMBA system
2.3. EASY_ML example AMBA system
2.4. ADK address map
3.1. Reset controller module components
3.2. Arbiter module components
3.3. Default slave module components
3.4. Master-to-slave multiplexor module components
3.5. Slave-to-master multiplexor module components
3.6. Retry slave module components
3.7. SMI components
3.8. BusMatrix module components
3.9. Example Bus Matrix design configuration
3.10. Region equations
3.11. Address map at different remap states
3.12. Decoder module components
3.13. System memory map
3.14. Ahb2Apb bridge module
3.15. Allocation of APB memory slots within EASY systems
3.16. AhbToApb bridge module
3.17. EBM module components
3.18. Example AHB-Lite core
3.19. Ahb2Ahb bridge
3.20. Ahb2AhbSyncDn bridge
3.21. Ahb2AhbSyncUp bridge
3.22. Ahb2AhbPass bridge
3.23. Applications of synchronous AHB-AHB bridges
3.24. System memory maps without address aliasing
3.25. Address-aliasing hardware
3.26. System memory maps with aliased addressing
3.27. System memory maps with piecewise addressing
3.28. Bidirectional bridging
3.29. Error cancel timing
3.30. Error cancel using ErrorCanc timing
3.31. Asynchronous AHB-AHB bridge module components
3.32. AHB-Lite to AHB wrapper
3.33. Interrupt controller components
3.34. ICPROTECTION Register bit assignments
3.35. ICITCR Register bit assignments
3.36. ICITIP1 Register bit assignments
3.37. ICITOP1 Register bit assignments
3.38. ICPERIPHID0-3 Register bit assignments
3.39. ICPCELLID0-3 Register bit assignments
3.40. Downsizer module
3.41. Funnel module
3.42. Typical funnel connection
4.1. Remap and pause module components
4.2. RPCPERIPHID0-3 Register bit assignment s
4.3. RPCPCELLID0-3 Register bit assignments
4.4. Example APB slave components
4.5. Peripheral to bridge multiplexor module components
4.6. Watchdog components
4.7. WDOGCONTROL Register bit assignments
4.8. WDOGRIS Register bit assignments
4.9. WDOGMIS Register bit assignments
4.10. WDOGLOCK Register bit assignments
4.11. WDOGITCR Register bit assignments
4.12. WDOGITOP Register bit assignments
4.13. WDOGPERIPHID0-3 Register bit assignments
4.14. WDOGPCELLID0-3 Register bit assignments
4.15. Dual input timer components
4.16. Free-running timer block
4.17. Prescale clock enable generation
4.18. TIMERXCONTROL Register bit assignments
4.19. TIMERXRIS Register bit assignments
4.20. TIMERXMIS Register bit assignments
4.21. TIMERITCR Register bit assignments
4.22. TIMERITOP Register bit assignments
4.23. Peripheral identification register bit assignments
4.24. PrimeCell identification register bit assignments
5.1. AHB external RAM module interface diagram
5.2. AHB internal memory module components
5.3. External ROM module interface diagram
5.4. Tube module interface diagram
5.5. File reader bus master
5.6. Write command timing
5.7. Read command timing
5.8. Sequential command timing
5.9. Busy transfer timing
5.10. Busy cycle timing
5.11. Idle transfer timing
5.12. Idle cycle timing
5.13. Poll command timing
5.14. Stimulus file conversion
5.15. Ticbox module interface diagram
A.1. AHB-Lite single-master system
A.2. AHB-Lite components

List of Tables

1.1. AMBA AHB signals
1.2. AMBA APB signals
3.1. Reset controller signals
3.2. Arbiter signals descriptions
3.3. Static memory bank select coding, Remap = 1
3.4. Test control signals during normal operation
3.5. Test control signals during test operation
3.6. Control vector bit definitions
3.7. Signal descriptions
3.8. Bus Matrix signals
3.9. Decoder module signals
3.10. AhbToAPB Bridge signals
3.11. Configurable options
3.12. Synchronous AHB-AHB bridge interface signals
3.13. Asynchronous AHB-AHB bridge interface signals
3.14. Interrupt standard configuration
3.15. Interrupt controller registers
3.16. ICIRQSTATUS Register bit assignments
3.17. ICFIQSTATUS Register bit assignments
3.18. ICRAWINTR Register bit assignments
3.19. ICINTSELECT Register bit assignments
3.20. ICINTENABLE Register bit assignments
3.21. ICINTENCLEAR Register bit assignments
3.22. ICSOFTINT Register bit assignments
3.23. ICSOFTINTCLEAR Register bit assignments
3.24. ICPROTECTION Register bit assignments
3.25. ICVECTADDR Register bit assignments
3.26. ICDEFVECTADDR Register bit assignments
3.27. ICITCR Register bit assignments
3.28. ICITIP1 Register bit assignments
3.29. ICITIP2 Register bit assignments
3.30. ICITOP1 Register bit assignments
3.31. ICITOP2 Register bit assignments
3.32. ICPERIPHID0 Register bit assignments
3.33. ICPERIPHID1 Register bit assignments
3.34. ICPERIPHID2 Register bit assignments
3.35. ICPERIPHID3 Register bit assignments
3.36. ICPCELLID0 Register bit assignments
3.37. ICPCELLID1 Register bit assignments
3.38. ICPCELLID2 Register bit assignments
3.39. ICPCELLID3 Register bit assignments
3.40. Interrupt controller signals
3.41. Narrow transfer handling
3.42. Address line modification and data routing
3.43. Signal mapping when downsizer module is activated
3.44. Downsizer interface signals
3.45. Funnel interface signals
4.1. Remap and pause register summary
4.2. RPCPERIPHID0 Register bit assignments
4.3. RPCPERIPHID1 Register bit assignments
4.4. RPCPERIPHID2 Register bit assignments
4.5. RPCPERIPHID3 Register bit assignments
4.6. RPCPCELLID0 Register bit assignments
4.7. RPCPCELLID1 Register bit assignments
4.8. RPCPCELLID2 Register bit assignments
4.9. RPCPCELLID3 Register bit assignments
4.10. Remap and pause controller signals
4.11. Example APB slave memory map
4.12. Peripheral ID format
4.13. Watchdog unit register summary
4.14. WDOGCONTROL Register bit assignments
4.15. WDOGRIS Register bit assignments
4.16. WDOGMIS Register bit assignments
4.17. WDOGLOCK Register bit assignments
4.18. WDOGITCR Register bit assignments
4.19. WDOGITOP Register bit assignments
4.20. WDOGPERIPHID0 Register bit assignments
4.21. WDOGPERIPHID1 Register bit assignments
4.22. WDOGPERIPHID2 Register bit assignments
4.23. WDOGPERIPHID3 Register bit assignments
4.24. WDOGPCELLID0 Register bit assignments
4.25. WDOGPCELLID1 Register bit assignments
4.26. WDOGPCELLID2 Register bit assignments
4.27. WDOGPCELLID3 Register bit assignments
4.28. Watchdog unit signals
4.29. Timer register summary
4.30. TIMERXCONTROL Register bit assignments
4.31. TIMERXRIS Register bit assignments
4.32. TIMERXMIS Register bit assignments
4.33. TIMERITCR Register bit assignments
4.34. TIMERITOP Register bit assignments
4.35. TIMERPERIPHID0 Register bit assignments
4.36. TIMERPERIPHID1 Register bit assignments
4.37. TIMERPERIPHID2 Register bit assignments
4.38. TIMERPERIPHID3 Register bit assignments
4.39. TIMERPCELLID0 Register bit assignments
4.40. TIMERPCELLID1 Register bit assignments
4.41. TIMERPCELLID2 Register bit assignments
4.42. TIMERPCELLID3 Register bit assignments
4.43. Timer signals
5.1. User-defined settings for the external RAM module
5.2. External RAM module signals
5.3. User-defined settings for the internal RAM module
5.4. User-defined settings for the external ROM module
5.5. External ROM module signals
5.6. Tube module signals
5.7. Stimulus command syntax
5.8. Command fields
5.9. Characters supported by comment command
5.10. Compatibility between versions of FRM and
5.11. Compatibility between versions of stimulus file and
5.12. Preprocessor command-line options
5.13. error messages
5.14. warnings
5.15. Numbering scheme for bit 7, severity
5.16. Numbering scheme for bits [6:4] and [3:2], error and warning type and subtype
5.17. Numbering scheme for bits [1:0], enumerator
5.18. Ticbox module signals
5.19. User-defined settings for the Ticbox module
A.1. AHB-Lite interchangeability

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AFebruary 2003First release
Revision BOctober 2003Updated for r3p0 release
Revision CAugust 2007C for r3p0 release
Copyright © 2003, 2007 ARM Limited. All rights reserved.ARM DDI 0243C