ETM10RV™ Technical Reference Manual 3.2.2. ETM10RV control inputs

3.2.2. ETM10RV control inputs

The ETM10RV control inputs are described in the following sections:

ETMDATAVALID[1:0]

This signal qualifies the data on the ETMDATA[63:0] bus as follows:

ETMDATAVALID[1] qualifies ETMDATA[63:32]
ETMDATAVALID[0] qualifies ETMDATA[31:0].

ETMCORECTL[30:0]

The control signals from the ARM1026EJ-S processor comprise ETMCORECTL[30:0]. The control signals present on this bus are described in Table 3.3.

Note

All the signals described in Table 3.3 are valid in the Write (WR) stage of the ARM1026EJ-S pipeline, unless specified otherwise.

Table 3.3. Signals on the ETMCORECTL[30:0] bus

Signal name	Bit number	Description	Qualified by
ITBit	[0]	Asserted when ARM1026EJ-S processor is in Thumb state (valid in ME).	InMREQ/ForcePF
InMREQ	[1]	Current address on the IA bus is for a valid instruction fetch.	None
ForcePF	[2]	Current address on the IA bus is a target for an indirect branch.	None
InstValid	[5]	Asserted once per executed instruction. Not asserted for mispredicted branches, because these are fetched but not executed.	None
BpValid	[3]	Asserted once per executed branch phantom. When asserted, a branch phantom is present in the Execute stage of the processor pipeline.	None
CCFail	[6]	Current instruction failed its condition codes.	InstValid
BpCCFail	[4]	Branch phantom failed its condition codes.	BpValid
Tbit	[7]	Asserted when ARM1026EJ-S processor is in Thumb state (valid in ME).	InstValid
ETMBranch	[8]	Last instruction executed is an indirect branch.	Asserted before or coincident with ForcePF
R15HoldMe	[9]	Stall signal for the address given on R15EX.	None
UpdatesContextID	[10]	Current instruction is updating the CONTEXT ID.	InstValid
DnMREQ	[11]	Qualifies the Data Address bus, DA.	None
DMAS[1:0]	[13:12]	Load or store data size.	DnMREQ
ETMSwap	[14]	Indicates a 64-bit store to a big-endian memory device.	DnMREQ
DnRW	[15]	Data request read/write signal (LOW for read cycle).	DnRW
HUMACK	[16]	Valid load miss data is present on the data bus this cycle.	None
LSCMInit	[17]	Current instruction is an LSM instruction.	InstValid unless it is a Java instruction
LSCM	[18]	LSM is in progress in the Load/Store Unit.	DnMREQ
MISSCNT[1:0]	[20:19]	The number of load misses that are outstanding.	None, transitions indicate new miss.
TrueException	[21]	Current instruction is an exception (interrupt, reset, or abort). Asserted on all exceptions.	InstValid for ARM & Thumb instructions. JInstEnd for Java instructions.
DAbort	[22]	Data request aborted.	DnMREQ
IgnoreMREQ	[23]	Current instruction is a preload and must not be traced.	InstValid
JBit	[24]	Asserted when ARM1026EJ-S processor is in Java mode.	InstValid
IJBit	[25]	Asserted when ARM1026EJ-S processor is in Java mode.	ForcePF
JInstEnd	[26]	Qualifies end of a Java instruction.	None
ETMRSVALID	[27]	Indicates that the target address for a stack operation is on the ETMR15BP bus.	None
Exception	[28]	Asserted to indicate cancelling exceptions.	InstValid for ARM and Thumb instructions. JInstEnd for Java instructions.
ExType[1:0]	[30:29]	Indicates the type of exception.	InstValid for ARM and Thumb instructions. JInstEnd for Java instructions.

Copyright © 2002, 2003 ARM Limited. All rights reserved.	ARM DDI 0245B
Non-Confidential
PDF version