ETM10RV TechnicalReference Manual

Revision: r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the ETM10RV
1.2. Standard configuration
2. Accessing the ETM10RV Registers
2.1. Debug interface
2.2. ETM10RV registers
3. Integrating the ETM10RV
3.1. About integrating the ETM10RV
3.1.1. ETM10RV to ARM1026EJ-S connectionguide
3.2. ARM1026EJ-S trace interface
3.2.1. ETM10RV data path inputs
3.2.2. ETM10RV control inputs
3.3. System control signals
3.3.1. Debug
3.3.2. Using the PWRDOWN signal
3.3.3. The SYSOPT bus
3.4. Clocks and resets
3.4.1. GCLK
3.4.2. DBGTCKEN
3.4.3. NRESET
3.4.4. NTRST
3.5. ETM10RV ASIC interface signals
3.6. DAP interface wiring
3.6.1. Multiprocessor DAP structure
3.7. Trace port interfacing
3.7.1. Trace port logic
3.7.2. Single-processor tracing
3.7.3. Dual-processor tracing
3.7.4. Supported trace clocking modes
3.7.5. PCB design guidelines
4. Design for Test
4.1. About DFT
4.1.1. DFT modes
4.1.2. Clock gating
4.1.3. Asynchronous signals
4.2. ETM10RV test wrapper
4.2.1. Dedicated input wrapper cells
4.2.2. Dedicated output wrapper cells
4.2.3. Shared wrapper cells
4.2.4. Scan test reset control
4.3. Test modes and ports
4.3.1. Selecting a test mode
4.3.2. Wrapper scan chains
4.3.3. Internal test mode
4.3.4. External test mode
4.3.5. Functional mode
4.4. IDDQ
4.4.1. Set up all logic on one or more Vdd planessimultaneously
4.4.2. Partition the logic and set up eachlogic section individually
4.4.3. Put each core on a separate Vdd planeand set up the logic for one Vdd
5. Implementation-defined Behavior
5.1. ETM architecture version
5.1.1. ETM10RV ID register
5.2. Precise TraceEnable events
5.3. Parallel instruction execution
5.4. Comparator behavior
5.5. Supported port modes and sizes onETM10RV
5.6. Exact match bit
5.6.1. Trace filtering signals and aborts
5.6.2. Instruction address comparisons
5.6.3. Data access comparisons
5.7. Synchronization behavior during datasuppression
5.8. Java data instructions
5.9. Configuration code register
5.10. Context ID tracing
6. Tracing Dynamically-loaded Images
6.1. About tracing dynamically-loaded code
6.2. Software support for context ID
6.3. Hardware support for context ID
7. Physical Trace Port Signal Guidelines
7.1. About trace port signal quality
7.2. ASIC pad selection, placement, andpackage type
7.3. PCB design guidelines
7.3.1. Dedicated trace port
7.3.2. Shared trace port
7.4. EMI compliance
7.5. Further references
A. Signal Descriptions
A.1. Functional signals
A.2. DFT signals
Glossary

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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 03September 2002 First release r0p0
Revision B 30September 2003 Second release r0p0. Updated withcorrection to Table 4-5.
Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0245B
Non-Confidential