3.3.12. Register 15, Debug Register

The Debug Control Register is used to force specific cache behavior required for debug. This register has read-only or read/write permission, and can only be accessed by a secure access. If a non-secure access tries to read or write to this register, a DECERR response is returned and the register is not updated.

Figure 3.14 shows the register bit assignments.

Figure 3.14. Debug Control Register bit assignments

Table 3.37 shows the register bit assignments.

Table 3.37. Debug Control Register bit assignments

[2]SPNIDENReads value of SPNIDEN input.
[1]DWB: Disable write-back (force WT)

0 = Enable write-back behavior. This is the default.

1 = Force write-through behavior.

[0]DCL: Disable cache linefill

0 = Enable cache linefills. This is the default.

1 = Disable cache linefills.

Forcing write-through behavior

If you set the DWB bit to 1, it forces the cache controller to treat all cacheable accesses as though they were in a write-through no write-allocate region of memory. The setting of the DWB bit overrides the access attributes. If the cache contains dirty cache lines, these remain dirty while the DWB bit is set, unless they are written back because of a write-back eviction after a linefill, or because of an explicit clean operation.

While the DWB bit is set, lines that are clean are not marked as dirty if they are updated. This functionality enables a debugger to download code or data to external memory, without the requirement to clean part or the entire cache to ensure that the code or data being downloaded has been written to external memory.

If you have set the DWB bit to 1, and a write is made to a cache line that is dirty, then both the cache line and the external memory are updated with the write data.

Disabling cache linefills

If you set the DCL bit to 1, no allocation occurs on either reads or writes. This mode of operation is required for debug so that the memory image, as seen by the processor, can be examined in a non-invasive manner. Cache hits read data words from the cache, and cache misses from a cacheable region read words directly from memory.


The forcing write-through and disabling cache linefills features have priority over other features acting on cachability properties, such as Force Write-Allocate, exclusive cache configuration.

Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A