3.3.9. Register 7, Cache Maintenance Operations

The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. If the operation is specific to the Way or Index/Way, their behavior is presented in the following manner:

Secure access

The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines.

Non-secure access

The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified.

Also depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the PA, the behavior is presented in the following manner:

Table 3.14 shows the cache maintenance operations. They are executed by writing to the Cache Operations Register 7. See also Table 3.15.

Table 3.14. Maintenance operations

OperationBase offsetTypeBit assignment format
Cache Sync0x730RW-
Invalidate Line by PA0x770RWSee Figure 3.9
Invalidate by Way0x77CRWSee Figure 3.11
Clean Line by PA0x7B0RWSee Figure 3.9
Clean Line by Index/Way0x7B8RWSee Figure 3.10
Clean by Way0x7BCRWSee Figure 3.11
Clean and Invalidate Line by PA0x7F0RWSee Figure 3.9
Clean and Invalidate Line by Index/Way0x7F8RWSee Figure 3.10
Clean and Invalidate by Way0x7FCRWSee Figure 3.11

Figure 3.9 shows the PA format.

Figure 3.9. Physical address format

Figure 3.10 shows the Index or Way format.

Figure 3.10. Index/way format

Note

For a 16-way implementation, all four bits [31:28] are used. If the 16-way option is not enabled, bit [31] is reserved.

Atomic operations

The following are atomic operations:

  • Clean Line by PA or by Index/Way

  • Invalidate Line by PA

  • Clean and Invalidate Line by PA or by Index/Way

  • Cache Sync.

These operations stall the slave ports until they are complete.

Background operations

The following operations are run as background tasks:

  • Invalidate by Way

  • Clean by Way

  • Clean and Invalidate by Way.

Note

If lockdown by line is implemented, the Unlock All Lines operation is also a background operation.

Writing to the register starts the operation on the Ways set to 1 in bits [15:0]. When a Way bit is set to 1, it is reset to 0 when the corresponding way is totally cleaned or invalidated. You must poll Register 7 to see when the operation is complete, indicated by all bits cleared.

Figure 3.11 shows the Format C lockdown. You can select multiple ways at the same time, by setting the Way bits to 1.

Figure 3.11. Format C lockdown

Note

For a 16-way implementation, all bits [15:0] are used. If the 16-way option is not enabled, bits [15:8] are reserved.

During background operations, the software must not access these ways. Any write to a configuration and control register while a background operation is running results in a SLVERR response.

During background operations, the targeted way is considered to be locked, this means that no allocation occurs to that way on read or write misses. Read or write hits are permitted to access the way. No hazard detection is performed on data returned, additionally the data written might not be coherent with L3. This is because it is unknown whether the background operation has completed. In summary, there can still be dirty lines after a cache clean operation.

Note

Data accessed by the L1 master is still correct.

Software must not perform a clean instruction on a region when it contains active data, that is, data accessed during the clean operation. To ensure that a clean operation is completed, mask the interrupts. Also ensure that the software polls on the Cache Operation Register to check if the operation is complete.

Table 3.15 shows the cache maintenance operations.

Table 3.15. Cache maintenance operations

OperationDescription
Cache Sync Drain the STB to L3 and/or L2 cache. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty.
Invalidate Line by PA Specific L2 cache line is marked as not valid.
Invalidate by WayInvalidate all data in specified ways, including dirty data. An Invalidate by way while selecting all cache ways is equivalent to invalidating all cache entries. Completes as a background task with the way(s) locked, preventing allocation.
Clean Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged.
Clean Line by Index/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged.
Clean by WayWrites each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not dirty. The valid bits are unchanged. Completes as a background task with the way(s) locked, preventing allocation.
Clean and Invalidate Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid.
Clean and Invalidate Line by Index/WayWrite the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid.
Clean and Invalidate by WayWrites each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not valid. Completes as a background task with the way(s) locked, preventing allocation.

During all operations where a cache line is cleaned or invalidated the non-secure bit is unchanged and is treated in the same way as the address.

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