3.3.7. Register 2, Event Counter Value Registers

The Event Counter Value Registers are read and write registers. These registers enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register. This register can be accessed by secure and non-secure operations. Table 3.9 shows the register bit assignments. These register can only be written to when bits [5:2] of the Event Counter Configuration Registers are set to Counter Disabled.

Table 3.9. Event Counter 1 Value Register bit assignments

[31:0]Counter valueTotal of the event selected.
Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A