3.2. Summary of registers

Table 3.1 shows the register map for the cache controller.

Table 3.1. Cache controller register map

RegisterReadsWritesSecure
0Cache ID and Cache TypeIgnoredNS/S
1ControlControl

Write S

Read NS/S

2Interrupt/Counter Control RegistersInterrupt/Counter Control RegistersNS/S
3-6ReservedReserved-
7Cache Maintenance OperationsCache Maintenance OperationsSecure bit of access affects operation
8ReservedReserved-
9Cache LockdownCache LockdownSecure bit of access affects operation
10-11ReservedReserved-
12Address FilteringAddress Filtering

Write S

Read NS/S

13-14ReservedReserved-
15DebugDebug

Write S

Read S

All register addresses in the cache controller are fixed relative to the base address. Table 3.2 shows the registers in base offset order.

Table 3.2. Summary of cache controller registers

RegisterName

Base offset

Type

Reset value

Description
r0Cache ID0x000RO0x410000C0[1]Register 0, Cache ID Register
r0Cache Type0x004RO0x1C100100[2]Register 0, Cache Type Register
r1Control0x100RW0x00000000Register 1, Control Register
r1Auxiliary Control0x104RW0x02020FFF[2]Register 1, Auxiliary Control Register
r2Event Counter Control0x200RW0x00000000Register 2, Event Counter Control Register
r2Event Counter1 Configuration0x204RW0x00000000Register 2, Event Counter Configuration Registers
r2Event Counter0 Configuration0x208RW0x00000000
r2Event Counter1 Value0x20CRW0x00000000Register 2, Event Counter Value Registers
r2Event Counter0 Value0x210RW0x00000000
r2Interrupt Mask[3]0x214RW0x00000000Register 2, Interrupt Registers
r2Masked Interrupt Status[3]0x218RO0x00000000
r2Raw Interrupt Status[3]0x21CRO0x00000000
r2Interrupt Clear[3]0x220WO0x00000000
r7Cache Sync0x730RW0x00000000Register 7, Cache Maintenance Operations
r7Invalidate Line By PA0x770RW0x00000000
r7Invalidate by Way0x77CRW0x00000000
r7Clean Line by PA0x7B0RW0x00000000
r7Clean Line by Index/Way0x7B8RW0x00000000
r7Clean by Way0x7BCRW0x00000000
r7Clean and Invalidate Line by PA0x7F0RW0x00000000
r7Clean and Invalidate Line by Index/Way0x7F8RW0x00000000
r7Clean and Invalidate by Way0x7FCRW0x00000000
r9Data Lockdown 0 by Way0x900RW0x00000000Register 9, Cache Lockdown
r9Instruction Lockdown 0 by Way0x904RW0x00000000Register 9, Cache Lockdown
r9Data Lockdown 1 by Way[4]0x908RW0x00000000
r9Instruction Lockdown 1 by Way[4]0x90CRW0x00000000
r9Data Lockdown 2 by Way[4]0x910RW0x00000000
r9Instruction Lockdown 2 by Way[4]0x914RW0x00000000
r9Data Lockdown 3 by Way[4]0x918RW0x00000000
r9Instruction Lockdown 3 by Way[4]0x91CRW0x00000000
r9Data Lockdown 4 by Way[4]0x920RW0x00000000
r9Instruction Lockdown 4 by Way[4]0x924RW0x00000000
r9Data Lockdown 5 by Way[4]0x928RW0x00000000
r9Instruction Lockdown 5 by Way[4]0x92CRW0x00000000
r9Data Lockdown 6 by Way[4]0x930RW0x00000000
r9Instruction Lockdown 6 by Way[4]0x934RW0x00000000
r9Data Lockdown 7 by Way[4]0x938RW0x00000000
r9Instruction Lockdown 7 by Way[4]0x93CRW0x00000000
r9Lockdown by Line Enable[5]0x950RW0x00000000
r9Unlock All Lines by Way[5]0x954RW0x00000000
r12Address Filtering Start0xC00RW0x00000000Register 12, Address Filtering
r12Address Filtering End0xC04RW0x00000000
r15Debug Control Register0xF40RW0x00000000Register 15, Debug Register

[1] This value is pin dependent, depending on how external CACHEID pins are tied.

[2] This value is pin dependent, depending on how external WAYSIZE and ASSOCIATIVITY pins are tied.

[3] The cache interrupt registers are those that can be accessed by secure and non-secure operations.

[4] These registers are implemented if the option pl310_LOCKDOWN_BY_MASTER is enabled. Otherwise, they are unused.

[5] These registers are implemented if the option pl310_LOCKDOWN_BY_LINE is enabled. Otherwise, they are unused.

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