3.3.10. Register 9, Cache Lockdown

The Cache Lockdown Register is a read-write register. This register prevents new addresses being allocated and also prevents the data in the set ways from being evicted. It also enables the cache controller to filter data from instructions or data transactions.

Note

Register 7 operations that invalidate, clean, or clean and invalidate cache contents affect locked-down cache lines as normal.

This register has read-only or read and write permission, depending on the security you have selected for the register access and on the Non-Secure Lockdown Enable bit in the Auxiliary Control Register. Table 3.16 shows the different settings of the Cache Lockdown Register.

Table 3.16. Cache lockdown

Security of register accessNon-Secure Lockdown Enable bitPermission
Secure

0, this is the default value

1

Read and write

Read and write

Non-Secure

0, this is the default value

1

Read only

Read and write

On reset the Non-Secure Lockdown Enable bit is set to 0 and Lockdown Registers are not permitted to be modified by non-secure accesses. In that configuration, if a non-secure access tries to write to those registers, the write response returns a DECERR response. This decode error results in the registers not being updated.

When permitted, the non-secure lockdown functionality can be identical to the secure one.

There are two lockdown schemes, line-based and way-based.

Cache lockdown by line

This feature is optional, and can be enabled using the pl310_LOCKDOWN_BY_LINE parameter. You can program a period of time during which all allocated cache lines are marked as locked and are then considered as locked, preventing them from being evicted. The locking period is enabled when bit [0] of the Lockdown by Line Enable Register is set. See Table 3.17.

Table 3.17. Lockdown by Line Enable Register bit assignments

BitsFieldDescription
[31:1]ReservedSBZ/RAZ
[0]lockdown_by_line_enable

0 = Lockdown by line disabled. This is the default.

1 = Lockdown by line disabled.

The locked status of each cache line is given by the optional bit [21] of the Tag RAM. During a locking period, the choice of way for allocations is described in Cache lockdown by way.

You can unlock all lines marked as locked by the Lock by Line mechanism, by using the Unlock All Lines operation, which is a background operation. You can check the status of this operation by reading the Unlock All Lines register. See Table 3.18.

While an Unlock All Lines operation is in progress, you cannot launch a background cache maintenance operation. If attempted, a SLVERR is returned.

Table 3.18. Unlock All Lines Register bit assignments

BitsFieldDescription
[31:16]ReservedSBZ/RAZ
[15:0]unlock_all_lines_by_way_operation

For all bits:

0 = Unlock all lines disabled. This is the default.

1 = Unlock all lines operation in progress for the corresponding way.

Cache lockdown by way

To only use selected cache ways within a SET, Lockdown format C, defined by the ARM Architecture Reference Manual, provides a method to restrict the replacement algorithm used on cache allocations. Using this method, you can fetch code or load data into the L2 cache and protect it from being evicted. Alternatively the method can be used to reduce cache pollution. See Figure 3.11. The 32-bit ADDR cache address consists of the following fields: < TAG > < INDEX > < WORD > < BYTE >

Whenever the cache lookup occurs, the Index defines where in the cache ways to look, and the number of ways defines the number of locations with the same Index. This is called a Set. Therefore an 16-way set associative cache has 16 locations where an address with INDEX (A) can exist.

Note

The number of locations are also known as lines.

If the cache lookup misses and a cache linefill is required, there are 16 possible locations where the new line can be placed. Lockdown format C restricts the cache replacement algorithm to only use a subset of the 16 possible locations.

If the Lockdown by Master feature is enabled through the pl310_LOCKDOWN_BY_MASTER option, you can lock ways differently based on different master IDs, provided by AR/WUSERSx[7:5]. If the Lockdown by Master feature is not enabled, you can only define a different lockdown mechanism for data and instructions.

The locking configurability is shown in Table 3.19 to Table 3.34. To apply lockdown, set each bit to 1 to lock each respective Way. For example, set Bit [0] for Way 0, Bit [1] for Way 1.

Table 3.19. Data Lockdown 0 Register, offset 0x900

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK000Use when AR/WUSERSx[7:5] = 000

Table 3.20. Instruction Lockdown 0 Register, offset 0x904

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK000Use when AR/WUSERSx[7:5] = 000

Table 3.21. Data Lockdown 1 Register, offset 0x908

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK001Use when AR/WUSERSx[7:5] = 001

Table 3.22. Instruction Lockdown 1 Register, offset 0x90C

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK001Use when AR/WUSERSx[7:5] = 001

Table 3.23. Data Lockdown 2 Register, offset 0x910

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK010Use when AR/WUSERSx[7:5] = 010

Table 3.24. Instruction Lockdown 2 Register, offset 0x914

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK010Use when AR/WUSERSx[7:5] = 010

Table 3.25. Data Lockdown 3 Register, offset 0x918

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK011Use when AR/WUSERSx[7:5] = 011

Table 3.26. Instruction Lockdown 3 Register, offset 0x91C

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK011Use when AR/WUSERSx[7:5] = 011

Table 3.27. Data Lockdown 4 Register, offset 0x920

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK100Use when AR/WUSERSx[7:5] = 100

Table 3.28. Instruction Lockdown 4 Register, offset 0x924

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK100Use when AR/WUSERSx[7:5] =100

Table 3.29. Data Lockdown 5 Register, offset 0x928

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK101Use when AR/WUSERSx[7:5] = 101

Table 3.30. Instruction Lockdown 5 Register, offset 0x92C

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK101Use when AR/WUSERSx[7:5] = 101

Table 3.31. Data Lockdown 6 Register, offset 0x930

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK110Use when AR/WUSERSx[7:5] = 110

Table 3.32. Instruction Lockdown 6 Register, offset 0x934

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK110Use when AR/WUSERSx[7:5] = 110

Table 3.33. Data Lockdown 7 Register, offset 0x938

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]DATALOCK111Use when AR/WUSERSx[7:5] = 111

Table 3.34. Instruction Lockdown 7 Register, offset 0x93C

BitsFieldDescription
[31:16]ReservedRAZ
[15:0]INSTRLOCK111Use when AR/WUSERSx[7:5] = 111

Note

  • If the pl310_16_WAYS option is not implemented, bits [15:8] are reserved in all the Data and Instruction Lockdown registers.

  • The Data and Instruction Lockdown 1-7 registers are not used if the option pl310_LOCKDOWN_BY_MASTER is not enabled.

Replacement strategy

The cache controller uses a pseudo-random replacement strategy. A deterministic replacement strategy can be achieved when you use the lockdown registers.

The pseudo-random replacement strategy fills empty, unlocked ways first. If a line is completely full, the victim is chosen as the next unlocked way.

If you require a deterministic replacement strategy, the lockdown registers are used to prevent ways from being allocated. For example, if the L2 size is 256KB, and each way is 32KB, and a piece of code is required to reside in two ways of 64KB, with a deterministic replacement strategy, then ways 1-7 must be locked before the code is filled into the L2 cache. If the first 32KB of code is allocated into way 0 only, then way 0 must be locked and way 1 unlocked so that the second half of the code can be allocated in way 1.

There are two lockdown registers, one for data and one for instructions, if so required, you can separate data and instructions into separate ways of the L2 cache.

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