3.3.1. Register 0, Cache ID Register

The Cache ID Register is a read-only register and returns the 32-bit device ID code. This register reads off the CACHEID input bus. The value is specified by system integrator.

Figure 3.1 shows the register bit assignments.

Figure 3.1. Cache ID Register bit assignments

Table 3.3 shows the register bit assignments.

Table 3.3. Cache ID Register bit assignments

[31:24]Implementer0x41 (ARM)
[15:10]CACHE ID-
[9:6]Part number
[5:0]RTL release0x0


  • Part number 0x3 denotes ARM PL310 Level 2 Cache Controller

  • RTL release 0x0 denotes r0p0 code of the cache controller. See the Release Note for the value of these bits for other releases.

Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A