3.3.2. Register 0, Cache Type Register

The Cache Type Register is a read-only register and returns the 32-bit cache type. This register provides data for cache type, cache size, way size, associativity and cache line length, in instruction and data format. The cache size is a product of:

Figure 3.2 shows the register bit assignments.

Figure 3.2. Cache Type Register bit assignments

Table 3.4 shows the register bit assignments.

Table 3.4. Cache Type Register bit assignments

BitsFieldSub-fieldComments
[31:29]SBZ 000
[28:25]ctype 

11xy, where:

x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0

y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0.See Register 9, Cache Lockdown for information on the lockdown features.

[24]H 0 - unified[1]
[23:19]Dsize -
[23]SBZ/RAZ0
[22:20]L2 cache way sizeRead from Auxiliary Control Register [19:17]
[19]SBZ/RAZ0
[18]L2 associativity Read from Auxiliary Control Register [16]
[17:14]SBZ 0
[13:12]L2 cache line length 00 - 32 bytes
[11:7]Isize -
[11]SBZ/RAZ0
[10:8]L2 cache way sizeRead from Auxiliary Control Register [19:17]
[7]SBZ/RAZ0
[6]L2 associativity Read from Auxiliary Control Register [16]
[5:2]SBZ 0
[1:0]L2 cache line length 00 - 32 bytes

[1] 1 = Harvard.

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