3.3.4. Register 1, Auxiliary Control Register

The Auxiliary Control Register is a read and write register. This register enables you to configure:

The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR.

Figure 3.4 shows the register bit assignments.

Figure 3.4. Auxiliary Control Register bit assignments

Table 3.6 shows the register bit assignments.

Table 3.6. Auxiliary Control Register bit assignments

BitsFieldDescription
[31:30]ReservedSBZ/RAZ
[29]Instruction prefetch enable[1]

0 = Instruction prefetching disabled. This is the default.

1= Instruction prefetching enabled.

[28]Data prefetch enable[1]

0 = Data prefetching disabled. This is the default.

1= Data prefetching enabled.

[27]Non-secure interrupt access control

0 = Interrupt Clear (0x220) and Interrupt Mask (0x214) can only be modified or read with secure accesses. This is the default.

1 = Interrupt Clear (0x220) and Interrupt Mask (0x214) can be modified or read with secure or non-secure accesses.

[26]Non-secure lockdown enable

0 = Lockdown registers cannot be modified using non-secure accesses. This is the default.

1 = Non-secure accesses can write to the lockdown registers.

[25]ReservedSBO/RAO
[24:23]Force write allocate

00 = Use AWCACHE attributes for WA. This is the default.

01 = Force no allocate, set WA bit always 0.

10 = Override AWCACHE attributes, set WA bit always 1 (all cacheable write misses become write allocated).

11 = Internally mapped to 00. See Cache operation for more details.

[22]Shared attribute override enable

0 = Treats shared accesses as specified in Shared attribute. This is the default.

1 = Shared attribute internally ignored.

[21]Parity enable

0 = Disabled. This is the default.

1 = Enabled.

[20]Event monitor bus enable

0 = Disabled. This is the default.

1 = Enabled.

[19:17]Way-size

000 = Reserved, internally mapped to 16KB.

001 = 16KB. This is the default.

010 = 32KB.

011 = 64KB.

100 = 128KB.

101 = 256KB.

110 = 512KB.

111 = Reserved, internally mapped to 512 KB.

[16:13]Associativity

0 = 8-way. This is the default.

1 = 16-way.

[15:13]ReservedSBZ/RAZ
[12]Exclusive cache configuration

0 = Disabled. This is the default.

1 = Enabled, see Exclusive cache configuration.

[11:9]ReservedSBZ/RAZ
[8:6]Cycles of latency for tag RAM

000 = 1 cycle of latency, there is no additional latency.

001 = 2 cycles of latency.

010 = 3 cycles of latency.

011 = 4 cycles of latency.

100 = 5 cycles of latency.

101 = 6 cycles of latency.

110 = 7 cycles of latency.

111 = 8 cycles of latency. This is the default.

See Cache controller compiled RAM latencies for more information.

[5:3]Cycles of latency for data RAM writes
[2:0]Cycles of latency for data RAM reads

[1] When enabled, as soon as a cacheable read transaction is received by one of the slave ports, a cache lookup is done on the sequentially following cache line. In case of miss, the cache line is prefetched from L3 and allocated into the L2 cache. The prefetch mechanism is not launched in the case of 4KB boundary crossing.

Cache controller compiled RAM latencies

The cache controller resets assuming the slowest compiled RAMs are being used. This means eight cache controller clock cycles are used for each access. In terms of reads, this means that the read data is sampled eight clock edges after the edge on which the RAM samples the read request. Using this arrangement, the shortest latency is one. You can program the latencies for each RAM in the Auxiliary Control Register. You must only program this register when the L2 cache is not enabled. Figure 3.5 shows a compiled RAM latency.

Figure 3.5. Compiled RAM latency examples for reads

Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A
Non-Confidential