3.3.3. Register 1, Control Register

The Control Register is a read and write register. This register enables or disables the cache controller. This register must be written using a secure access. It can be read using either a secure or a NS access. Writing to this register with a NS access causes a write response signal with a DECERR response, and the register is not updated, only permitting a secure access to enable or disable the cache controller.

When receiving a transaction to enable or disable the cache by modifying this register the cache controller follows the described sequence. This prevents any unpredictable behavior if there are subsequent writes to any of the L2 registers.

  1. Lock slave ports and wait for all outstanding transactions to complete and all buffers to be empty by performing a cache sync.

  2. Update register.

  3. Return write response.

Figure 3.3 shows the register bit assignments.

Figure 3.3. Control Register bit assignments

Table 3.5 shows the register bit assignments.

Table 3.5. Control Register bit assignments

BitsFieldDescription
[31:1]ReservedSBZ/RAZ
[0]L2 Cache enable

0 = L2 Cache is disabled. This is the default value.

1 = L2 Cache is enabled.

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