3.3.5. Register 2, Event Counter Control Register

The Event Counter Control Register is a read and write register. This register permits the event counters to be enabled and reset when required. This register can be accessed by secure and non-secure operations. Figure 3.6 shows the register bit assignments.

Figure 3.6. Event Counter Control Register bit assignments

Table 3.7 shows the register bit assignments.

Table 3.7. Event Counter Control Register bit assignments

BitsFieldDescription
[31:3]ReservedSBZ/RAZ
[2:1]Counter reset

Always Read as zero Corresponding counters are reset when the bit is written to by 1:

Bit 2 = Event Counter1 reset

Bit 1 = Event Counter0 reset.

[0]Event counter enable

0 = Event Counting Disable. This is the default.

1 = Event Counting Enable.

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