3.3.8. Register 2, Interrupt Registers

There are four interrupt registers:

Figure 3.8 shows the register bit assignments.

Figure 3.8. Interrupt Register bit assignments

Interrupt Mask Register

The Interrupt Mask Register is a read and write register. This register enables or masks interrupts from being triggered on the external pins of the cache controller. Figure 3.8 shows the register bit assignments. The bit assignments enables the masking of the interrupts on both their individual outputs and the combined L2CCINTR line. Clearing a bit by writing a 0, disables the interrupt triggering on that pin. All bits are cleared by a reset. You must write to the register bits with a 1 to enable the generation of interrupts. Non-secure access to this register is dependent on Auxiliary Control Register bit [27].

Table 3.10 shows the register bit assignments.

Table 3.10. Interrupt Mask Register bit assignments

BitsFieldDescription
[31:9]ReservedSBZ/RAZ
[8]DECERR: DECERR from L3

1 = Enable.

0 = Masked. This is the default.

[7]SLVERR: SLVERR from L3
[6]ERRRD: Error on L2 data RAM (Read)
[5]ERRRT: Error on L2 tag RAM (Read)
[4]ERRWD: Error on L2 data RAM (Write)
[3]ERRWT: Error on L2 tag RAM (Write)
[2]PARRD: Parity Error on L2 data RAM (Read)
[1]PARRT: Parity Error on L2 tag RAM (Read)
[0]ECNTR: Event Counter1/0 Overflow Increment

Masked Interrupt Status Register

The Masked Interrupt Status Register is a read-only register. This register is a read-only that enables the interrupt status that includes the masking logic. This register can be accessed by secure and non-secure operations. The register gives an AND function of the raw interrupt status with the values of the interrupt mask register. All the bits are cleared by a reset.

Table 3.11 shows the register bit assignments.

Table 3.11. Masked Interrupt Status Register bit assignments

BitsFieldDescription
[31:9]ReservedRAZ
[8]DECERR: DECERR from L3

Bits read can be HIGH or LOW:

If the bits read HIGH, they reflect the status of the input lines triggering an interrupt.If bits read LOW, either no interrupt has been generated or the interrupt is masked.

[7]SLVERR: SLVERR from L3
[6]ERRRD: Error on L2 data RAM (Read)
[5]ERRRT: Error on L2 tag RAM (Read)
[4]ERRWD: Error on L2 data RAM (Write)
[3]ERRWT: Error on L2 tag RAM (Write) 
[2]PARRD: Parity Error on L2 data RAM (Read) 
[1]PARRT: Parity Error on L2 tag RAM (Read) 
[0]ECNTR: Event Counter1/0 Overflow Increment 

Raw Interrupt Status Register

The Raw Interrupt Status Register is a read-only register that enables the interrupt status that excludes the masking logic. This register can be accessed by secure and non-secure operations. All the bits are cleared by a reset.

Table 3.12 shows the register bit assignments.

Table 3.12. Raw Interrupt Status Register bit assignments

BitsFieldDescription
[31:9]ReservedRAZ
[8]DECERR: DECERR from L3

Bits read can be HIGH or LOW:

If the bits read HIGH, they reflect the status of the input lines triggering an interrupt.If bits read LOW, no interrupt has been generated.

[7]SLVERR: SLVERR from L3
[6]ERRRD: Error on L2 data RAM (Read)
[5]ERRRT: Error on L2 tag RAM (Read)
[4]ERRWD: Error on L2 data RAM (Write)
[3]ERRWT: Error on L2 tag RAM (Write)
[2]PARRD: Parity Error on L2 data RAM (Read)
[1]PARRT: Parity Error on L2 tag RAM (Read)
[0]ECNTR: Event Counter1/0 Overflow Increment

Interrupt Clear Register

The Interrupt Clear Register is a write-only register and all bits are cleared by a reset. Non-secure access to this register is dependent on Auxiliary Control Register bit [27].

Table 3.13 shows the register bit assignments.

Table 3.13. Interrupt Clear Register bit assignments

BitsFieldDescription
[31:9]ReservedRAZ
[8]DECERR: DECERR from L3

When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register

When a bit is written as 0, it has no effect

[7]SLVERR: SLVERR from L3
[6]ERRRD: Error on L2 data RAM (Read)
[5]ERRRT: Error on L2 tag RAM (Read)
[4]ERRWD: Error on L2 data RAM (Write)
[3]ERRWT: Error on L2 tag RAM (Write)
[2]PARRD: Parity Error on L2 data RAM (Read)
[1]PARRT: Parity Error on L2 tag RAM (Read)
[0]ECNTR: Event Counter1/0 Overflow Increment
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