3.3.6. Register 2, Event Counter Configuration Registers

The Event Counter Configuration Registers are read and write registers. These registers enable event counter 1 and 0 to be driven by a specific event. When the event occurs it causes the counter1 or 0 to increment. The counter event source signals are described in Cache event monitoring. This register can be accessed by secure and NS operations. Figure 3.7 shows the register bit assignments.

Figure 3.7. Event Counter Configuration Register bit assignments

Table 3.8 shows the register bit assignments.

Table 3.8. Event Counter Configuration Register bit assignments

BitsFieldDescription
[31:6]ReservedSBZ/RAZ
[5:2]Counter event sourceEventEncoding
Counter Disabled0000
CO0001
DRHIT0010
DRREQ0011
DWHIT0100
DWREQ0101
DWTREQ0110
IRHIT0111
IRREQ1000
WA1001
Counter Disabled1010-1111
[1:0]Event counter interrupt generation

00 = Disabled. This is the default.

01 = Enabled: Increment condition.

10 = Enabled: Overflow condition.

11 = Interrupt generation is disabled.

Note

When the SPNIDEN input pin is LOW the event counters only increment on non-secure events, secure events are not counted unless the SPNIDEN pin signal is configured HIGH.

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