2.10. MBIST support

MBIST is used for testing the RAMs connected to the cache controller. ARM can supply an MBIST controller as a separate block, or you can design your own MBIST controller. Only one RAM can be accessed by the MBIST port at a time.

The data RAM is 256 bits wide, and the size of the MBISTDIN and MBISTDOUT buses on the cache controller is 64 bits, so four reads and four writes are required for each index of the data RAM. The cache controller handles this by using two of the MBISTADDR address pins as a double word select for each index of the data RAM.

The MBIST controller must be able to account for the different latencies of the RAMs. Data read, data write, and tag read or write accesses can all be programmed with different access latencies.

If present, the tag parity bit is tested at the same time as tag RAMs. Parity bits are considered as an extra bit on tag data bus.

Figure 2.3 shows the cache controller MBIST interface.

Figure 2.3. MBIST interface for 16-way implementation, with parity, without lockdown by line

Note

MBIST is a secure feature. The signals are available at the top level of the design for test, but must not be bonded out in production.

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