1.2. Typical system configuration

The cache controller works efficiently with ARM processors that implement AXI interfaces. It directly interfaces on the data and instruction interface. The internal pipelining of the cache controller is optimized to enable the processors to operate at the same clock frequency.

The cache controller supports:

Figure 1.2 shows an example of a cache controller with two slave ports and two master ports interfaced to an ARM processor.

Figure 1.2. Example cache controller interfaced to an ARM processor

You can configure the cache controller to use one or two master ports. Table 1.3 shows what each master port is used for.

Table 1.3. Master port transactions for a two master port system

Master port 0Master port 1

Non-cacheable reads from S0

Linefills from S0

Write allocations reads from STB

Non-bufferable writes from S0

Bufferable writes from STB

Evictions from EB

Non-cacheable reads from S1

Linefills from S1

Write allocations reads from STB

Non-bufferable writes from S1

Bufferable writes from STB

Evictions from EB

Note

  • Table 1.3 does not take address filtering into account.

  • In a one master port system, master port 1 is not implemented. All master port 0 transactions apply to both S0 and S1.

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