A.7. MBIST interface

MBIST interfaceTable A.11 shows the MBIST interface signals.

Table A.11. MBIST interface signals

SignalTypeDescription
MBISTADDR[19:0]InputMBIST address
MBISTCE[17:0]InputMBIST RAM chip enable
MBISTDCTL[19:0]OutputMBIST data out mux control
MBISTDIN[63:0]InputMBIST data in
MBISTWE[31:0]InputMBIST write enable
MBISTONInputMBIST mode enable
MBISTDOUT[63:0]OutputMBIST data out
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