1.1. About the cache controller

The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a recognized method of improving the performance of ARM-based systems when significant memory traffic is generated by the processor. By definition a secondary cache assumes the presence of a Level 1 or primary cache, closely coupled or internal to the processor.

Memory access is fastest to L1 cache, followed closely by L2 cache. Memory access is typically significantly slower with L3 main memory. Table 1.1 shows typical sizes and access times for different types of memory.

Table 1.1. Typical memory sizes and access times

Memory typeTypical sizeTypical access time
Processor registers128B1 cycle
On-chip L1 cache32KB1-2 cycle(s)
On-chip L2 cache256KB8 cycles
Main memory (L3) dynamic RAMMB or GB[1]30-100 cycles
Back-up memory (hard disk) (L4)MB or GB> 500 cycles

[1] Size limited by the processor core addressing, for example a 32-bit processor without memory management can directly address 4GB of memory.

The cache controller features:

The cache controller is a unified, physically addressed, physically tagged cache with up to 16 ways. You can lock the replacement algorithm on a way basis, enabling the associativity to be reduced from 16-way down to one-way, direct mapped. The cache controller does not have snooping hardware to maintain coherency between caches, so you must maintain coherency by software.

Figure 1.1 shows a top level diagram of the cache controller.

Figure 1.1. Top level diagram

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