A.4.1. Data RAM interface

Data RAM interfaceTable A.7 shows the data RAM interface signals.

Table A.7. Data RAM interface signals

SignalTypeDescription

DATAADDR[17:0][1]

DATAADDR[16:0][2]

OutputData RAM address
DATACSOutputData RAM chip select
DATAEN[31:0]OutputData RAM byte write enables
DATAERRInputData RAM error
DATAnRWOutputData RAM write control signal
DATAPRD[31:0][3]InputData RAM parity read data
DATAPWD[31:0][3]OutputData RAM parity write data
DATARD[255:0]InputData RAM read data
DATAWAITInputData RAM wait
DATAWD[255:0]OutputData RAM write data

[1] For 16-way implementation.

[2] For 8-way implementation.

[3] Optional. Only present if pl310_PARITY is defined.

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