A.2. Configuration

Table A.2 shows the configuration signals.

Table A.2. Configuration signals

ASSOCIATIVITY InputAssociativity for Auxiliary Control Register
CACHEID[5:0] InputCache controller cache ID
CFGBIGEND InputBig-endian mode for accessing configuration registers
RDATALAT[2:0] OutputLatency for read data RAM from Auxiliary Control Register
REGFILEBASE[19:0] InputBase address for accessing configuration registers
SE InputDFT test enable, held HIGH during serial shift of scan chains and LOW for capture
TAGLAT[2:0] OutputLatency for tag RAM from Auxiliary Control Register
WAYSIZE[2:0] InputSize of ways for Auxiliary Control Register
WDATALAT[2:0] OutputLatency for write data RAM from Auxiliary Control Register
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