A.3.3. Master port 0

Table A.5 shows the master port 0 signals.

Table A.5. Master port 0 signals

SignalTypeDescription
ARADDRM0[31:0]OutputAddress bus
ARBURSTM0[1:0]OutputBurst type
ARCACHEM0[3:0]OutputCache information
ARIDM0[`pl310_AXI_ID_MAX+2:0]OutputAddress ID
ARLENM0[3:0]OutputBurst length
ARLOCKM0[1:0]OutputLock type
ARPROTM0[2:0]OutputProtection information
ARREADYM0InputAddress accepted
ARSIZEM0[2:0]OutputBurst size
ARVALIDM0OutputAddress valid
AWADDRM0[31:0]OutputAddress bus
AWBURSTM0[1:0]OutputBurst type
AWCACHEM0[3:0]OutputCache information
AWIDM0[`pl310_AXI_ID_MAX+2:0]OutputAddress ID
AWLENM0[3:0]OutputBurst length
AWLOCKM0[1:0]OutputLock type
AWPROTM0[2:0]OutputProtection information
AWREADYM0InputAddress accepted
AWSIZEM0[2:0]OutputBurst size
AWVALIDM0OutputAddress valid
BIDM0[`pl310_AXI_ID_MAX+2:0]InputWrite ID
BREADYM0OutputWrite response accepted
BRESPM0[1:0]InputWrite response
BVALIDM0InputWrite response valid
RDATAM0[63:0]InputRead data bus
RIDM0[`pl310_AXI_ID_MAX+2:0]InputRead ID
RLASTM0InputRead last transfer
RREADYM0OutputRead accepted
RRESPM0[1:0]InputRead response
RVALIDM0InputRead data valid
WDATAM0[63:0]OutputWrite data bus
WIDM0[`pl310_AXI_ID_MAX+2:0]OutputWrite ID
WLASTM0OutputWrite last transfer
WREADYM0InputWrite data accepted
WSTRBM0[7:0]OutputWrite strobes
WVALIDM0OutputWrite data valid
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