A.3.4. Master port 1

Table A.6 shows the master port 1 signals.

Table A.6. Master port 1 signals

SignalTypeDescription
ARADDRM1[31:0]OutputAddress bus
ARBURSTM1[1:0]OutputBurst type
ARCACHEM1[3:0]OutputCache information
ARIDM1[`pl310_AXI_ID_MAX+2:0]OutputAddress ID
ARLENM1[3:0]OutputBurst length
ARLOCKM1[1:0]OutputLock type
ARPROTM1[2:0]OutputProtection information
ARREADYM1InputAddress accepted
ARSIZEM1[2:0]OutputBurst size
ARVALIDM1OutputAddress valid
AWADDRM1[31:0]OutputAddress bus
AWBURSTM1[1:0]OutputBurst type
AWCACHEM1[3:0]OutputCache information
AWIDM1[`pl310_AXI_ID_MAX+2:0]OutputAddress ID
AWLENM1[3:0]OutputBurst length
AWLOCKM1[1:0]OutputLock type
AWPROTM1[2:0]OutputProtection information
AWREADYM1InputAddress accepted
AWSIZEM1[2:0]OutputBurst size
AWVALIDM1OutputAddress valid
BIDM1[`pl310_AXI_ID_MAX+2:0]InputWrite ID
BREADYM1OutputWrite response accepted
BRESPM1[1:0]InputWrite response
BVALIDM1InputWrite response valid
RDATAM1[63:0]InputRead data bus
RIDM1[`pl310_AXI_ID_MAX+2:0]InputRead ID
RLASTM1InputRead last transfer
RREADYM1OutputRead accepted
RRESPM1[1:0]InputRead response
RVALIDM1InputRead data valid
WDATAM1[63:0]OutputWrite data bus
WIDM1[`pl310_AXI_ID_MAX+2:0]OutputWrite ID
WLASTM1OutputWrite last transfer
WREADYM1InputWrite data accepted
WSTRBM1[7:0]OutputWrite strobes
WVALIDM1OutputWrite data valid
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