A.6. Cache interrupt

Table A.10 shows the cache interrupt signals.

Table A.10. Cache Interrupt signals

SignalTypeDescription
DECERRINTROutputDecode error received on master port from L3
ECNTRINTROutputEvent Counter Overflow/Increment
ERRRDINTROutputError on L2 data RAM read
ERRRTINTROutputError on L2 tag RAM read
ERRWDINTROutputError on L2 data RAM write
ERRWTINTROutputError on L2 data RAM write
L2CCINTROutputCombined Interrupt Output
PARRDINTROutputParity error on L2 data RAM read
PARRTINTROutputParity error on L2 tag RAM read
SLVERRINTROutputSlave error received on master port from L3
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