2.11.1. Data RAM

The data RAM shown in Figure 2.4 is organized as n-way 256-bit wide contiguous memories, where n is 8 or 16. It supports the following accesses:

Figure 2.4. Data RAM organization for 16 ways

A DATAWAIT signal is added to the Data RAM interface to provide support for ECC through an external block. When the Data RAM latency is reached, the cache controller still waits for the data or error if the wait signal is asserted. The data or error is then sampled when the wait signal is deasserted.

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