2.9.6. Cache event monitoring

The cache controller supplies pins for event monitoring of the L2 cache. The signals on the pins are held HIGH for one cycle each time the event occurs.

An additional input signal, SPNIDEN, configures the level of debug where:

When the signal on the SPNIDEN pin is LOW the event bus and event counters only output or count non-secure events.

When the signal on the SPNIDEN pin is HIGH the event bus and event counters output or count non-secure and secure events.

You can poll SPNIDEN through the SPNIDEN bit in the Debug Control Register. You must perform a cache sync operation before debug or any analysis that relies on this signal. Synchronizers for the signal are added to prevent any issues from asynchronous domain control.

The event monitoring bus is enabled by writing to the event monitoring bus enable bit in the Auxiliary Control Register. Table 2.10 shows the event pins.

Table 2.10. Event pins

PinDescription
COEviction (CastOUT) of a line from the L2 cache.
DRHITData read hit in the L2 cache.
DRREQData read lookup to the L2 cache. Subsequently results in a hit or miss.
DWHITData write hit in the L2 cache.
DWREQData write lookup to the L2 cache. Subsequently results in a hit or miss.
DWTREQData write lookup to the L2 cache with Write-Through attribute. Subsequently results in a hit or miss.
IRHITInstruction read hit in the L2 cache.
IRREQInstruction read lookup to the L2 cache. Subsequently results in a hit or miss.
SPNIDENSecure privileged non-invasive debug enable.
WAAllocation into the L2 cache caused by a write (with Write-Allocate attribute) miss.
Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A
Non-Confidential