2.2. Cache attributes

Table 2.3 describes the AWCACHE[3:0] and ARCACHE[3:0] signals as described in the AMBA AXI Protocol Specification, and the ARMv6 and ARMv7 equivalent meaning.

Table 2.3. AWCACHE and ARCACHE definitions

AWCACHE/ARCACHEAXI meaningARMv6 and ARMv7 equivalent
WARACB
0000Noncacheable, nonbufferable Strongly ordered
0001Bufferable onlyDevice
0010Cacheable but do not allocateOuter noncacheable
0011Cacheable and bufferable, do not allocateOuter noncacheable
0110Cacheable write-through, allocate on readOuter write-through, no allocate on write
0111Cacheable write-back, allocate on readOuter write-back, no allocate on write
1010Cacheable write-through, allocate on write-
1011Cacheable write-back, allocate on write-
1110Cacheable write-through, allocate on both read and write-
1111Cacheable write-back, allocate on both read and writeOuter write-back, write allocate

Note

  • The shared attribute AW/RUSERSx[0] is not described in this table. Its behavior is explained in Cache operation, under Shared attribute.

  • The cache controller supports all AXI cache attributes, even if the processor does not use all of them

  • If the cache controller receives cacheable fixed transactions, AWBURST/ARBURSTSx = 00, the results are unpredictable.

  • Table 2.3 does not show AXI locked and exclusive accesses.

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