2.9.3. Cache configurability

Table 2.8 shows how the cache controller can be configured.

Table 2.8. Cache controller cache configurability


Enabled by

Range of options

Default value

Default option
Cache way sizeRegister or WAYSIZE[2:0] input16KB, 32KB, 64KB, 128KB, 256KB, 512KB00116KB
Number of cache waysRegister or ASSOCIATIVITY input8, 16[1]08 ways
LatencyRegister1, 2, 3, 4, 5, 6, 7, 81118 cycles of latency
Removal of slave port 1Verilog `define pl310_S1Commented or uncommentedCommentedNo slave port 1
Removal of master port 1Verilog `define pl310_M1Commented or uncommentedCommentedNo master port 1
Parity logicVerilog `define pl310_PARITYCommented or uncommentedCommentedNo parity logic
Lockdown by master[2]Verilog `define pl310_LOCKDOWN_BY_MASTERCommented or uncommentedCommentedNo lockdown by master
Lockdown by line[2]Verilog `define pl310_LOCKDOWN_BY_LINECommented or uncommentedCommentedNo lockdown by line
AXI ID width on slave portsVerilog `define pl310_AXI_ID_MAX <value>>=156 AXI ID bits on slave ports and 8 on master ports

[1] 16-way associativity must be enabled using the pl310_16_WAYS verilog `define.

[2] If this feature is selected, you must specify if it is exclusive.


If a single slave port, AXI S1, is configured it is expected that only a single master port, AXI M1, is configured.

Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A