2.11.2. Tag RAM

The tag RAM is shown in Figure 2.5. There is one tag RAM for each way of the L2 cache. A tag RAM is organized as a 23-bit, 22-bit, or 21-bit wide memory:

The NS bit takes the value of 1 for NS data, and 0 for secure data.

Note

You require a 23-bit wide memory to support both parity and lockdown by line option. You require a 22-bit wide memory to support either the parity option or the lockdown by line option.

Figure 2.5. Tag RAM organization for 16 ways, with parity, without lockdown by line

A TAGWAIT signal is added to the tag RAM interface to provide support for ECC through an external block. When the tag RAM latency is reached, the cache controller still waits for the tags or error if the wait signal is asserted. The tags or error are then sampled when the wait signal is deasserted.

Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0246A
Non-Confidential