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Table B.6 shows the Data RAM signal timing parameters.
Table B.6. Data RAM
| Port name | I/O type | Maximum constraint |
|---|---|---|
| DATAADDR[16:0] | Output | 70% |
| DATACLKEN | Input | 30% |
| DATACLKOUT | Output | 50% |
| DATACLKOUTEN | Output | 50% |
| DATACS | Output | 70% |
| DATAEN[31:0] | Output | 70% |
| DATAERR | Input | 50% |
| DATAnRW | Output | 70% |
| DATAPEN[31:0] | Output | 70% |
| DATAPnRW | Output | 70% |
| DATAPRD[31:0] | Input | 50% |
| DATAPWD[31:0] | Output | 70% |
| DATARD[255:0] | Input | 50% |
| DATAWD[255:0] | Output | 70% |
| Copyright © 2007, 2008 ARM Limited. All rights reserved. | ARM DDI 0246B |
| Non-Confidential | |
| PDF version | |
| Home > AC Parameters > RAMs signal timing parameters > Data RAM |