PrimeCell Level 2 Cache Controller (PL310) Technical Reference ManualRevision: r1p0
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2.9.10. Cacheable read requests on AXI slave ports

Table 2.12 shows the error signalling cases and effects when there are cacheable read requests on the AXI salve ports.

Table 2.12. Cacheable read requests on AXI slave ports

CaseEffect
Tag parity or RAM error on tag readAn error is flagged through the PARRTINTR/ERRRTINTR interrupt signals.
Data RAM error on data readAn error is flagged through the PARRTINTR/ERRRTINTR interrupt signals.
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